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Some GPIO connected LEDs have inverted polarity.
Introduce new config option: CONFIG_GPIO_LED_INVERTED_TABLE for the
specifying the inverted GPIO LEDs list and add support for this in the
gpio_led driver.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Ilya Ledvich <ilya@compulab.co.il>

Add a check for the gpio_request() function return value and do not try
to configure the GPIO if the gpio_request() call fails.
Also, print an error message indicating the gpio_request() has failed.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Ilya Ledvich <ilya@compulab.co.il>

The CONFIG_GPIO_LED symbol does not have any documentation in the README
file. Document the CONFIG_GPIO_LED symbol.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>

In the case of not having CONFIG_CMD_HASH but having CONFIG_CMD_CRC32
enabled (and not CONFIG_CRC32_VERIFY), we end up in this part of the
code path on hash_command().  However, we will only have exactly 3 args
here, and 3 > 3 is false, and we will not try and store the hash at the
address given as arg #3.  The next problem however is that we've been
moving argv around so the third value is now in argv[0] not argv[3].

Confirmed on AM335x Beaglebone White.
Signed-off-by: Tom Rini <trini@ti.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

HOSTOS is defined and exported at the top Makefile.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

SPL_BIN is already defined in spl/Makefile
and it is used only in spl/Makefile.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

CONFIG_IXP4XX_NPE is defined only for CPU ixp.
It is not necessary to filter by CPU ixp.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

CONFIG_FMAN_ENET is defined only for CPU mpc85xx.
We do not need to filter by CPU mpc85xx.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

We do not need to handle $(LIBBOARD) and $(LIBS) separately.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

- Descend into drivers/fpga/ only when CONFIG_FPGA=y
  - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

The support for COBJS, COBJS-y, SOBJS, SOBJS-y, GLCOBJS, GLSOBJS
from scripts/Makefile.build.
Going forward we need to use Kbuild style consistently.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Board config.mk do not need to add -DCONFIG_SYS_TEXT_BASE
to CPPFLAGS because the top level config.mk does instead.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Commit 309a292e

 deleted OXC board, but
missed to remove the standalone example specific to OXC board.

eepro100_eeprom.c has been an orphan file for a long term.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Commit 7e8c53d7

 removed eNET board but missed to
add eNET to README.scrapyard.
This commit adds it for the record.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Graeme Russ <graeme.russ@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Thomas Chou <thomas@wytron.com.tw>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Since commit c2dd0d45 and 45bf0585

 introduced
the new cache maintainance framework to ARM,
CONFIG_L2_OFF has not been used at all.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

In 6789e84e

 we update u-boot-spl.lds for OMAP to ensure we include
adapter information, as we use i2c during SPL.  However, the regex used
also means we included commands that may have been built.  On omap5_uevm
this leads to a failure as we include the command from the do_tca642x
command, and fail to link.  The fix is to restrict our regex to only the
i2c list parts.
Signed-off-by: Tom Rini <trini@ti.com>

The physical base address of the NOR flash is 0x1e000000
on the Malta boards. The hardware also maps the first 4MiB
of the flash into the 0x1fc00000-0x1fffffff range.

Currently, U-Boot uses the mapped address to access the
flash, which does not work in recent qemu versions.

Since commit a427338b222b43197c2776cbc996936df0302f51
(mips_malta: correct reading MIPS revision at 0x1fc00010)
writing to the mapped address space causes a CPU exception.
Due to the exception, U-Boot hangs during boot when it tries
to detect the CFI flash chip.

Use the correct physical address for the MALTA_FLASH_BASE
constant to fix the problem. In order to avoid relocation
problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE
constants.

The change makes it possible to start U-Boot on a Malta
board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also
works on older versions (tested with 1.1.1, 1.2.2, 1.4.2,
1.5.3).
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>

When indexing freqProcessor[] we use the first
value in the cpu's "reg" property, which on
new e6500 cores IDs the threads.
But freqProcessor[] should be indexed with a
core index so, when fixing "the clock-frequency"
cpu node property, access the freqProcessor[]
with the core index derived from the "reg' property.
If we don't do this, last half of the "cpu" nodes
will have broken "clock-frequency" values.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: York Sun <yorksun@freescale.com>

Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets like:

  fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf
                             0xffffffd1 0xffffffd3
                             0xffffffd5 0xffffffd7
                             0xffffffd9 0xffffffdb>;

The update consists in adding a parameter to the
function that builds the list to specify the base
liodn.
On PCI v2.4 use the old base = 256 and, on PCI 3.0
where some of the PCIE liodns are larger than 256,
use a base = 1024. The version check is based on
the PCI controller's version register.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>

The liodn for the T4240's PCIE controller is no longer set
through a register in the guts register block but with one
in the PCIE register block itself.
Use the already existing SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>

Define base addresse for both MPH(USB1) and DR(USB2) controllers
for MPC834x socs
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>