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Commit a839ce06 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini
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board: dave: delete unused source files 

Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andrea Marson <andrea.marson@dave-tech.it>
parent d62bb61f
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board/dave/PPChameleonEVB/fpgadata.c deleted 100644 → 0
View file @ d62bb61f
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board/dave/common/fpga.c deleted 100644 → 0
View file @ d62bb61f
/*
* (C) Copyright 2001-2003
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <command.h>
/* ------------------------------------------------------------------------- */
#ifdef FPGA_DEBUG
#define DBG(x...) printf(x)
#else
#define DBG(x...)
#endif /* DEBUG */
#define MAX_ONES 226
#ifdef CONFIG_SYS_FPGA_PRG
# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/
# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
#else
# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
#endif
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
#define SET_FPGA(data) out32(GPIO0_OR, data)
#define FPGA_WRITE_1 { \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#define FPGA_WRITE_0 { \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG); /* set data to 0 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#if 0
static int fpga_boot (unsigned char *fpgadata, int size)
{
int i, index, len;
int count;
#ifdef CONFIG_SYS_FPGA_SPARTAN2
int j;
#else
unsigned char b;
int bit;
#endif
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = fpgadata[index];
DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
index += len + 3;
}
#ifdef CONFIG_SYS_FPGA_SPARTAN2
/* search for preamble 0xFFFFFFFF */
while (1) {
if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
&& (fpgadata[index + 2] == 0xff)
&& (fpgadata[index + 3] == 0xff))
break; /* preamble found */
else
index++;
}
#else
/* search for preamble 0xFF2X */
for (index = 0; index < size - 1; index++) {
if ((fpgadata[index] == 0xff)
&& ((fpgadata[index + 1] & 0xf0) == 0x30))
break;
}
index += 2;
#endif
DBG ("FPGA: configdata starts at position 0x%x\n", index);
DBG ("FPGA: length of fpga-data %d\n", size - index);
/*
* Setup port pins for fpga programming
*/
out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
DBG ("%s, ",
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
DBG ("%s\n",
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
/*
* Init fpga by asserting and deasserting PROGRAM*
*/
SET_FPGA (FPGA_CLK | FPGA_DATA);
/* Wait for FPGA init line low */
count = 0;
while (in32 (GPIO0_IR) & FPGA_INIT) {
udelay (1000); /* wait 1ms */
/* Check for timeout - 100us max, so use 3ms */
if (count++ > 3) {
DBG ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_INIT_LOW;
}
}
DBG ("%s, ",
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
DBG ("%s\n",
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
/* deassert PROGRAM* */
SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
/* Wait for FPGA end of init period . */
count = 0;
while (!(in32 (GPIO0_IR) & FPGA_INIT)) {
udelay (1000); /* wait 1ms */
/* Check for timeout */
if (count++ > 3) {
DBG ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_INIT_HIGH;
}
}
DBG ("%s, ",
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
DBG ("%s\n",
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
DBG ("write configuration data into fpga\n");
/* write configuration-data into fpga... */
#ifdef CONFIG_SYS_FPGA_SPARTAN2
/*
* Load uncompressed image into fpga
*/
for (i = index; i < size; i++) {
for (j = 0; j < 8; j++) {
if ((fpgadata[i] & 0x80) == 0x80) {
FPGA_WRITE_1;
} else {
FPGA_WRITE_0;
}
fpgadata[i] <<= 1;
}
}
#else /* ! CONFIG_SYS_FPGA_SPARTAN2 */
/* send 0xff 0x20 */
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_1;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
/*
** Bit_DeCompression
** Code 1 .. maxOnes : n '1's followed by '0'
** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
** 255 : '1'
*/
for (i = index; i < size; i++) {
b = fpgadata[i];
if ((b >= 1) && (b <= MAX_ONES)) {
for (bit = 0; bit < b; bit++) {
FPGA_WRITE_1;
}
FPGA_WRITE_0;
} else if (b == (MAX_ONES + 1)) {
for (bit = 1; bit < b; bit++) {
FPGA_WRITE_1;
}
} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
FPGA_WRITE_0;
}
FPGA_WRITE_1;
} else if (b == 255) {
FPGA_WRITE_1;
}
}
#endif /* CONFIG_SYS_FPGA_SPARTAN2 */
DBG ("%s, ",
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
DBG ("%s\n",
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
/*
* Check if fpga's DONE signal - correctly booted ?
*/
/* Wait for FPGA end of programming period . */
count = 0;
while (!(in32 (GPIO0_IR) & FPGA_DONE)) {
udelay (1000); /* wait 1ms */
/* Check for timeout */
if (count++ > 3) {
DBG ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_DONE;
}
}
DBG ("FPGA: Booting successful!\n");
return 0;
}
#endif /* 0 */
board/dave/common/pci.c deleted 100644 → 0
View file @ d62bb61f
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
#include <pci.h>
u_long pci9054_iobase;
#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */
#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */
/*-----------------------------------------------------------------------------+
| Subroutine: pci9054_read_config_dword
| Description: Read a PCI configuration register
| Inputs:
| hose PCI Controller
| dev PCI Bus+Device+Function number
| offset Configuration register number
| value Address of the configuration register value
| Return value:
| 0 Successful
+-----------------------------------------------------------------------------*/
int pci9054_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32* value)
{
unsigned long conAdrVal;
unsigned long val;
/* generate coded value for CON_ADR register */
conAdrVal = dev | (offset & 0xfc) | 0x80000000;
/* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
/* Note: *pResult comes back as -1 if machine check happened */
val = in32r(PCI_PRIMARY_CDR);
*value = (unsigned long) val;
out32r(PCI_PRIMARY_CAR, 0);
if ((*(unsigned long *)0x50000304) & 0x60000000)
{
/* clear pci master/target abort bits */
*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
}
return 0;
}
/*-----------------------------------------------------------------------------+
| Subroutine: pci9054_write_config_dword
| Description: Write a PCI configuration register.
| Inputs:
| hose PCI Controller
| dev PCI Bus+Device+Function number
| offset Configuration register number
| Value Configuration register value
| Return value:
| 0 Successful
| Updated for pass2 errata #6. Need to disable interrupts and clear the
| PCICFGADR reg after writing the PCICFGDATA reg.
+-----------------------------------------------------------------------------*/
int pci9054_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
unsigned long conAdrVal;
conAdrVal = dev | (offset & 0xfc) | 0x80000000;
*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
out32r(PCI_PRIMARY_CDR, value);
out32r(PCI_PRIMARY_CAR, 0);
/* clear pci master/target abort bits */
*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
return (0);
}
/*-----------------------------------------------------------------------
*/
#ifdef CONFIG_DASA_SIM
static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *_)
{
unsigned int iobase;
unsigned short status = 0;
unsigned char timer;
/*
* Configure PLX PCI9054
*/
pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
/* Check the latency timer for values >= 0x60.
*/
pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
if (timer < 0x60)
{
pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
}
/* Set I/O base register.
*/
pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
if (pci9054_iobase == 0xffffffff)
{
printf("Error: Can not set I/O base register.\n");
return;
}
}
#endif
static struct pci_config_table pci9054_config_table[] = {
#ifndef CONFIG_PCI_PNP
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
CONFIG_SYS_ETH_IOBASE,
PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
#ifdef CONFIG_DASA_SIM
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
pci_dasa_sim_config_pci9054 },
#endif
#endif
{ }
};
static struct pci_controller pci9054_hose = {
config_table: pci9054_config_table,
};
void pci_init(void)
{
struct pci_controller *hose = &pci9054_hose;
/*
* Register the hose
*/
hose->first_busno = 0;
hose->last_busno = 0xff;
/* System memory space */
pci_set_region(hose->regions + 0,
0x00000000, 0x00000000, 0x01000000,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI Memory space */
pci_set_region(hose->regions + 1,
0x00000000, 0xc0000000, 0x10000000,
PCI_REGION_MEM);
pci_set_ops(hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
pci9054_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
pci9054_write_config_dword);
hose->region_count = 2;
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
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