Initial revision

board/RPXClassic/RPXClassic.c

+/*
+ * (C)	Copyright 2001
+ * Stubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ * U-Boot port on RPXClassic LF (CLLF_BW31) board
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static unsigned char aschex_to_byte (unsigned char *cp);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
+	0x3FBFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
+	0x3FBFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
+	0x3FFFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
+	0x0CFFCC00, 0x33FFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
+	0x3FFFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXClassic\n");
+	return (0);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
+ *-----------------------------------------------------------------------------
+ */
+void board_get_enetaddr (uchar * enet)
+{
+	int i;
+	char buff[256], *cp;
+
+	/* Initialize I2C					*/
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM				*/
+	i2c_read (0x54, 0, 1, buff, 128);
+	i2c_read (0x54, 128, 1, buff + 128, 128);
+
+	/* Retrieve MAC address in buffer (key EA)		*/
+	for (cp = buff;;) {
+		if (cp[0] == 'E' && cp[1] == 'A') {
+			cp += 3;
+			/* Read MAC address			*/
+			for (i = 0; i < 6; i++, cp += 2) {
+				enet[i] = aschex_to_byte (cp);
+			}
+		}
+		/* Scan to the end of the record		*/
+		while ((*cp != '\n') && (*cp != 0xff)) {
+			cp++;
+		}
+		/* If the next character is a \n, 0 or ff, we are done.	*/
+		cp++;
+		if ((*cp == '\n') || (*cp == 0) || (*cp == 0xff))
+			break;
+	}
+
+#ifdef CONFIG_FEC_ENET
+	/* The MAC address is the same as normal ethernet except the 3rd byte	 */
+	/* (See the E.P. Planet Core Overview manual		*/
+	enet[3] |= 0x80;
+
+	/* Validate the fast ethernet tranceiver		*/
+	*((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
+	*((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
+	*((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
+	*((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
+#endif
+
+	printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
+		enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
+
+}
+
+void rpxclassic_init (void)
+{
+	/* Enable NVRAM */
+	*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
+
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size10;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000000;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - refresh twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size
+	 * try 10 column mode
+	 */
+
+	size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
+						SDRAM_MAX_SIZE);
+
+	return (size10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];			/* to make test non-destructive */
+	unsigned char i = 0;
+
+	memctl->memc_mamr = mamr_value;
+
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+static unsigned char aschex_to_byte (unsigned char *cp)
+{
+	u_char byte, c;
+
+	c = *cp++;
+
+	if ((c >= 'A') && (c <= 'F')) {
+		c -= 'A';
+		c += 10;
+	} else if ((c >= 'a') && (c <= 'f')) {
+		c -= 'a';
+		c += 10;
+	} else {
+		c -= '0';
+	}
+
+	byte = c * 16;
+
+	c = *cp;
+
+	if ((c >= 'A') && (c <= 'F')) {
+		c -= 'A';
+		c += 10;
+	} else if ((c >= 'a') && (c <= 'f')) {
+		c -= 'a';
+		c += 10;
+	} else {
+		c -= '0';
+	}
+
+	byte += c;
+
+	return (byte);
+}

board/RPXClassic/config.mk

+#
+# (C)  Copyright 2001
+# Stäubli Faverges - <www.staubli.com>
+# Pierre AUBERT  p.aubert@staubli.com
+# U-Boot port on RPXClassic LF (CLLF_BW31) board
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xff000000

board/RPXClassic/flash.c

+/*
+ * (C)  Copyright 2001
+ * Stubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ * U-Boot port on RPXClassic LF (CLLF_BW31) board
+ *
+ * RPXClassic uses Am29DL323B flash memory with 2 banks
+ *
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+
+        flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000) ;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+        case FLASH_AMDL323B:
+            printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n");
+            break;
+	default:
+            printf ("Unknown Chip Type\n");
+            break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+        /* Reset flash componeny                                             */
+        addr [0] = 0xf0f0f0f0;
+
+        /* Write auto select command: read Manufacturer ID */
+        addr[0xAAA] = 0xAAAAAAAA ;
+	addr[0x555] = 0x55555555 ;
+	addr[0xAAA] = 0x90909090 ;
+
+	value = addr[0] ;
+
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;		/* device ID		*/
+
+	switch (value & 0x00FF00FF) {
+        case (AMD_ID_DL323B & 0x00FF00FF):
+            info->flash_id += FLASH_AMDL323B;
+            info->sector_count = 71;
+            info->size = 0x01000000;            /* 16 Mb                     */
+
+            break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+        /* set sector offsets for bottom boot block type	*/
+        info->start[0] = base + 0x00000000;
+        info->start[1] = base + 0x00008000;
+        info->start[2] = base + 0x00010000;
+        info->start[3] = base + 0x00018000;
+        info->start[4] = base + 0x00020000;
+        info->start[5] = base + 0x00028000;
+        info->start[6] = base + 0x00030000;
+        info->start[7] = base + 0x00038000;
+        for (i = 8; i < info->sector_count; i++) {
+            info->start[i] = base + ((i-7) * 0x00040000) ;
+        }
+
+	/* check for protected sectors */
+        for (i = 0; i < 23; i++) {
+            /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+            /* D0 = 1 if protected */
+            addr = (volatile unsigned long *)(info->start[i]);
+            info->protect[i] = addr[4] & 1 ;
+	}
+        /* Check for protected sectors in the 2nd bank                       */
+        addr[0x100AAA] = 0xAAAAAAAA ;
+        addr[0x100555] = 0x55555555 ;
+        addr[0x100AAA] = 0x90909090 ;
+
+        for (i = 23; i < info->sector_count; i++) {
+            /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+            /* D0 = 1 if protected */
+            addr = (volatile unsigned long *)(info->start[i]);
+            info->protect[i] = addr[4] & 1 ;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank 1                      */
+		addr = (volatile unsigned long *)info->start[23];
+
+		*addr = 0xF0F0F0F0;	/* reset bank 2                      */
+
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+        return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */

board/RPXlite/RPXlite.c

+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * DRAM related UPMA register values are modified.
+ * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
+	0x3FBFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
+	0x3FBFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
+	0x3FFFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
+	0x0CFFCC00, 0x33FFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
+	0x3FFFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXlite\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    long int size10 ;
+
+    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Refresh clock prescalar */
+    memctl->memc_mptpr = CFG_MPTPR ;
+
+    memctl->memc_mar  = 0x00000000;
+
+	/* Map controller banks 1 to the SDRAM bank */
+    memctl->memc_or1 = CFG_OR1_PRELIM;
+    memctl->memc_br1 = CFG_BR1_PRELIM;
+
+    memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
+
+    udelay(200);
+
+    /* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr  = 0x80002230 ; /* SDRAM bank 0 - refresh twice */
+    udelay(1);
+
+    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+    udelay (1000);
+
+	/* Check Bank 0 Memory Size
+	 * try 10 column mode
+	 */
+
+	size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
+
+    return (size10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    volatile long int	 *addr;
+    ulong		  cnt, val;
+    ulong		  save[32];	/* to make test non-destructive */
+    unsigned char	  i = 0;
+
+    memctl->memc_mamr = mamr_value;
+
+    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	save[i++] = *addr;
+	*addr = ~cnt;
+    }
+
+    /* write 0 to base address */
+    addr = base;
+    save[i] = *addr;
+    *addr = 0;
+
+    /* check at base address */
+    if ((val = *addr) != 0) {
+	*addr = save[i];
+	return (0);
+    }
+
+    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	val = *addr;
+	*addr = save[--i];
+
+	if (val != (~cnt)) {
+	    return (cnt * sizeof(long));
+	}
+    }
+    return (maxsize);
+}

board/iphase4539/flash.c

+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Adapted for Interphase 4539 by Wolfgang Grandegger <wg@denx.de>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <flash.h>
+#include <asm/io.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+
+extern int hwc_flash_size(void);
+static ulong flash_get_size (u32 addr, flash_info_t *info);
+static int flash_get_offsets (u32 base, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_reset (u32 addr);
+
+#define out8(a,v) *(volatile unsigned char*)(a) = v
+#define in8(a)	  *(volatile unsigned char*)(a)
+#define in32(a)	  *(volatile unsigned long*)(a)
+#define iobarrier_rw() eieio()
+
+unsigned long flash_init (void)
+{
+	unsigned int i;
+	unsigned long flash_size = 0;
+	unsigned long bank_size;
+	unsigned int bank = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = 0;
+		flash_info[i].size = 0;
+	}
+
+	/* Initialise the BOOT Flash */
+	if (bank == CFG_MAX_FLASH_BANKS) {
+		puts ("Warning: not all Flashes are initialised !");
+		return flash_size;
+	}
+
+	bank_size = flash_get_size (CFG_FLASH_BASE, flash_info + bank);
+	if (bank_size) {
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
+    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_MAX_FLASH_SIZE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+			      flash_info + bank);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			      flash_info + bank);
+#endif
+
+		/* HWC protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_FLASH_BASE,
+			      CFG_FLASH_BASE + 0x10000 - 1,
+			      flash_info + bank);
+
+		flash_size += bank_size;
+		bank++;
+	} else {
+		puts ("Warning: the BOOT Flash is not initialised !");
+	}
+
+	return flash_size;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (u32 addr, flash_info_t *info)
+{
+	volatile uchar value;
+#if 0
+	int i;
+#endif
+
+	/* Write auto select command: read Manufacturer ID */
+	out8(addr + 0x0555, 0xAA);
+	iobarrier_rw();
+	udelay(10);
+	out8(addr + 0x02AA, 0x55);
+	iobarrier_rw();
+	udelay(10);
+	out8(addr + 0x0555, 0x90);
+	iobarrier_rw();
+	udelay(10);
+
+	value = in8(addr);
+	iobarrier_rw();
+	udelay(10);
+	switch (value | (value << 16)) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		flash_reset (addr);
+		return 0;
+	}
+
+	value = in8(addr + 1);			/* device ID		*/
+	iobarrier_rw();
+
+	switch (value) {
+	case AMD_ID_LV033C:
+		info->flash_id += FLASH_AM033C;
+		info->size = hwc_flash_size();
+		if (info->size > CFG_MAX_FLASH_SIZE) {
+			printf("U-Boot supports only %d MB\n",
+			       CFG_MAX_FLASH_SIZE);
+			info->size = CFG_MAX_FLASH_SIZE;
+		}
+		info->sector_count = info->size / 0x10000;
+		break;				/* => 4 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		flash_reset (addr);
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (!flash_get_offsets (addr, info)) {
+		flash_reset (addr);
+		return 0;
+	}
+
+#if 0
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		value = in8(info->start[i] + 2);
+		iobarrier_rw();
+		info->protect[i] = (value & 1) != 0;
+	}
+#endif
+
+	/*
+	 * Reset bank to read mode
+	 */
+	flash_reset (addr);
+
+	return (info->size);
+}
+
+static int flash_get_offsets (u32 base, flash_info_t *info)
+{
+	unsigned int i, size;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM033C:
+		/* set sector offsets for uniform sector type	*/
+		size = info->size / info->sector_count;
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + i * size;
+		}
+		break;
+	default:
+		return 0;
+	}
+
+	return 1;
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile u32 addr = info->start[0];
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if (s_first < 0 || s_first > s_last) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN ||
+	    info->flash_id > FLASH_AMD_COMP) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x80);
+	iobarrier_rw();
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = info->start[sect];
+			out8(addr, 0x30);
+			iobarrier_rw();
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = info->start[l_sect];
+	while ((in8(addr) & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+		iobarrier_rw();
+	}
+
+DONE:
+	/* reset to read mode */
+	flash_reset (info->start[0]);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile u32 addr = info->start[0];
+	ulong start;
+	int flag, i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((in32(dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* first, perform an unlock bypass command to speed up flash writes */
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x20);
+	iobarrier_rw();
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *)&data;
+		out8(addr, 0xA0);
+		iobarrier_rw();
+		out8(dest+i, data_ch[i]);
+		iobarrier_rw();
+		udelay(10); /* XXX */
+	}
+
+	/* we're done, now do an unlock bypass reset */
+	out8(addr, 0x90);
+	iobarrier_rw();
+	out8(addr, 0x00);
+	iobarrier_rw();
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((in32(dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+		iobarrier_rw();
+	}
+
+	flash_reset (addr);
+
+	return (0);
+}
+
+/*
+ * Reset bank to read mode
+ */
+static void flash_reset (u32 addr)
+{
+	out8(addr, 0xF0);	/* reset bank */
+	iobarrier_rw();
+}
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM033C:	printf ("AM29LV033C (32 Mbit, uniform sectors)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size % 0x100000 == 0) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size / 0x100000, info->sector_count);
+	}
+	else if (info->size % 0x400 == 0) {
+		printf ("  Size: %ld KB in %d Sectors\n",
+			info->size / 0x400, info->sector_count);
+	}
+	else {
+		printf ("  Size: %ld B in %d Sectors\n",
+			info->size, info->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}

board/sixnet/sixnet.c

+/*
+ * (C) Copyright 2001, 2002
+ * Dave Ellis, SIXNET, dge@sixnetio.com.
+ *  Based on code by:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * and other contributors to U-Boot. See file CREDITS for list
+ * of people who contributed to this  project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+#include <net.h>	/* for eth_init() */
+#include <rtc.h>
+#include "sixnet.h"
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+static long ram_size(ulong *, long);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ * returns 0 if recognized, -1 if unknown
+ */
+
+int checkboard (void)
+{
+	puts ("Board: SIXNET SXNI855T\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#error "SXNI855T has no PCMCIA port"
+#endif	/* CFG_CMD_PCMCIA */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_ 0xffffffff
+
+/* UPMB table for dual UART. */
+
+/* this table is for 50MHz operation, it should work at all lower speeds */
+const uint duart_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
+	0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
+
+	/* burst read. (offset 8 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
+	0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
+
+	/* burst write. (offset 20 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+};
+
+/* Load FPGA very early in boot sequence, since it must be
+ * loaded before the 16C2550 serial channels can be used as
+ * console channels.
+ *
+ * Note: Much of the configuration is not complete. The
+ *       stack is in DPRAM since SDRAM has not been initialized,
+ *       so the stack must be kept small. Global variables
+ *       are still in FLASH, so they cannot be written.
+ *	 Only the FLASH, DPRAM, immap and FPGA can be addressed,
+ *       the other chip selects may not have been initialized.
+ *       The clocks have been initialized, so udelay() can be
+ *       used.
+ */
+#define FPGA_DONE	0x0080	/* PA8, input, high when FPGA load complete */
+#define FPGA_PROGRAM_L	0x0040	/* PA9, output, low to reset, high to start */
+#define FPGA_INIT_L	0x0020	/* PA10, input, low indicates not ready	*/
+#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG))	/* FPGA port */
+
+int board_postclk_init (void)
+{
+
+	/* the data to load to the XCSxxXL FPGA */
+	static const unsigned char fpgadata[] = {
+# include "fpgadata.c"
+	};
+
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+#define porta (immap->im_ioport.iop_padat)
+	const unsigned char* pdata;
+
+	/* /INITFPGA and DONEFPGA signals are inputs */
+	immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
+
+	/* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
+	porta &= ~FPGA_PROGRAM_L;
+
+	/* Set FPGA as an output */
+	immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
+
+	/* delay a little to make sure FPGA sees it, really
+	 * only need less than a microsecond.
+	 */
+	udelay(10);
+
+	/* unassert /PROGRAM */
+	porta |= FPGA_PROGRAM_L;
+
+	/* delay while FPGA does last erase, indicated by
+	 * /INITFPGA going high. This should happen within a
+	 * few milliseconds.
+	 */
+	/* ### FIXME - a timeout check would be good, maybe flash
+	 * the status LED to indicate the error?
+	 */
+	while ((porta & FPGA_INIT_L) == 0)
+		; /* waiting */
+
+	/* write program data to FPGA at the programming address
+	 * so extra /CS1 strobes at end of configuration don't actually
+         * write to any registers.
+	 */
+	fpga = 0xff;		/* first write is ignored	*/
+	fpga = 0xff;		/* fill byte			*/
+	fpga = 0xff;		/* fill byte			*/
+	fpga = 0x4f;		/* preamble code		*/
+	fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
+	fpga = 0x4b;		/* field check code */
+
+	pdata = fpgadata;
+	/* while no error write out each of the 28 byte frames */
+	while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
+	       && pdata < fpgadata + sizeof(fpgadata)) {
+
+		fpga = 0x4f;	/* preamble code */
+
+		/* 21 bytes of data in a frame */
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++);
+
+		fpga = 0x4b;	/* field check code		*/
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0x4b;	/* extended write cycle
+				 * (actually 0x4b from bitgen.exe)
+				 */
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0xff;	/* extended write cycle		*/
+	}
+
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+
+#if 0 /* ### FIXME */
+	/* If didn't load all the data or FPGA_DONE is low the load failed.
+	 * Maybe someday stop here and flash the status LED? The console
+	 * is not configured, so can't print an error message. Can't write
+	 * global variables to set a flag (except gd?).
+	 * For now it must work.
+	 */
+#endif
+
+	/* Now that the FPGA is loaded, set up the Dual UART chip
+	 * selects. Must be done here since it may be used as the console.
+	 */
+	upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
+
+	memctl->memc_mbmr = DUART_MBMR;
+	memctl->memc_or5 = DUART_OR_VALUE;
+	memctl->memc_br5 = DUART_BR5_VALUE;
+	memctl->memc_or6 = DUART_OR_VALUE;
+	memctl->memc_br6 = DUART_BR6_VALUE;
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* base address for SRAM, assume 32-bit port,  valid */
+#define NVRAM_BR_VALUE   (CFG_SRAM_BASE | BR_PS_32 | BR_V)
+
+/*  up to 64MB - will be adjusted for actual size */
+#define NVRAM_OR_PRELIM  (ORMASK(CFG_SRAM_SIZE) \
+	| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
+/*
+ * Miscellaneous platform dependent initializations after running in RAM.
+ */
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	bd_t *bd = gd->bd;
+
+	memctl->memc_or2 = NVRAM_OR_PRELIM;
+	memctl->memc_br2 = NVRAM_BR_VALUE;
+
+	/* Is there any SRAM? Is it 16 or 32 bits wide? */
+
+	/* First look for 32-bit SRAM */
+	bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+
+	if (bd->bi_sramsize == 0) {
+	    /* no 32-bit SRAM, but there could be 16-bit SRAM since
+	     * it would report size 0 when configured for 32-bit bus.
+	     * Try again with a 16-bit bus.
+	     */
+	    memctl->memc_br2 |= BR_PS_16;
+	    bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+	}
+
+	if (bd->bi_sramsize == 0) {
+	    memctl->memc_br2 = 0;	/* disable select since nothing there */
+	}
+	else {
+	    /* adjust or2 for actual size of SRAM */
+	    memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
+	    bd->bi_sramstart = CFG_SRAM_BASE;
+	    printf("SRAM:  %lu KB\n", bd->bi_sramsize >> 10);
+	}
+
+
+	/* set standard MPC8xx clock so kernel will see the time
+	 * even if it doesn't have a DS1306 clock driver.
+	 * This helps with experimenting with standard kernels.
+	 */
+	{
+	    ulong tim;
+	    struct rtc_time tmp;
+
+	    rtc_get(&tmp);	/* get time from DS1306 RTC */
+
+	    /* convert to seconds since 1970 */
+	    tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+			 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+	    immap->im_sitk.sitk_rtck = KAPWR_KEY;
+	    immap->im_sit.sit_rtc = tim;
+	}
+
+#if 0
+	/* The code below is no longer valid since the prototype of
+	 * eth_init() and eth_halt() have been changed to support
+	 * multi-ethernet feature in U-Boot; the eth_initialize()
+	 * routine should be called before any access to the ethernet
+	 * callbacks.
+	 */
+
+	/* FIXME - for now init ethernet to force PHY special mode */
+	eth_init(bd);
+	eth_halt();
+#endif
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'.
+ *
+ * The memory size MUST be a power of 2 for this to work.
+ *
+ * The only memory modified is 4 bytes at offset 0. This is important
+ * since for the SRAM this location is reserved for autosizing, so if
+ * it is modified and the board is reset before ram_size() completes
+ * no damage is  done. Normally even the memory at 0 is preserved. The
+ * higher SRAM addresses may contain battery backed RAM disk data which
+ * must never be corrupted.
+ */
+
+static long ram_size(ulong *base, long maxsize)
+{
+    volatile long	*test_addr;
+    volatile long	*base_addr = base;
+    volatile long	*flash = (volatile long*)CFG_FLASH_BASE;
+    ulong		ofs;		/* byte offset from base_addr */
+    ulong		save;		/* to make test non-destructive */
+    ulong		junk;
+    long		ramsize = -1;	/* size not determined yet */
+
+    save = *base_addr;		/* save value at 0 so can restore */
+
+    /* is any SRAM present? */
+    *base_addr = 0x5555aaaa;
+
+    /* use flash read to modify data bus, since with no SRAM present
+     * the data bus may retain the value if our code is running
+     * completely in the cache.
+     */
+    junk = *flash;
+
+    if (*base_addr != 0x5555aaaa)
+	ramsize = 0;		/* no RAM present, or defective */
+    else {
+	*base_addr = 0xaaaa5555;
+	junk = *flash;		/* use flash read to modify data bus */
+	if (*base_addr != 0xaaaa5555)
+	    ramsize = 0;	/* no RAM present, or defective */
+    }
+
+    /* now size it if any is present */
+    for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
+	test_addr = (long*)((long)base_addr + ofs);	/* location to test */
+
+	*base_addr = ~*test_addr;
+	if (*base_addr == *test_addr)
+	    ramsize = ofs;	/* wrapped back to 0, so this is the size */
+    }
+
+    *base_addr = save;		/* restore value at 0 */
+    return (ramsize);
+}
+
+/* ------------------------------------------------------------------------- */
+/* sdram table based on the FADS manual                                      */
+/* for chip MB811171622A-100                                                 */
+
+/* this table is for 50MHz operation, it should work at all lower speeds */
+
+const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* precharge and Mode Register Set initialization (offset 5).
+	 * This is also entered at offset 6 to do Mode Register Set
+	 * without the precharge.
+	 */
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+        /* FADS had 0x1f27fc04, ...
+	 * but most other boards have 0x1f07fc04, which
+	 * sets GPL0 from A11MPC to 0 1/4 clock earlier,
+	 * like the single read.
+	 * This seems better so I am going with the change.
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_ };
+
+/* ------------------------------------------------------------------------- */
+
+#define	SDRAM_MAX_SIZE		0x10000000	/* max 256 MB SDRAM */
+
+/* precharge and set Mode Register */
+#define SDRAM_MCR_PRE    (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(1) | MCR_MAD(5))	/* 1 time at 0x05 */
+
+/* set Mode Register, no precharge */
+#define SDRAM_MCR_MRS    (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(1) | MCR_MAD(6))	/* 1 time at 0x06 */
+
+/* runs refresh loop twice so get 8 refresh cycles */
+#define SDRAM_MCR_REFR   (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(2) | MCR_MAD(0x30))	/* twice at 0x30  */
+
+/* MAMR values work in either mamr or mbmr */
+/* 8 column SDRAM */
+#define SDRAM_MAMR_8COL  /* refresh at 50MHz */				  \
+			 ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE		  \
+			 | MAMR_AMA_TYPE_0	/* Address MUX 0 */	  \
+			 | MAMR_DSA_1_CYCL	/* 1 cycle disable */	  \
+			 | MAMR_G0CLA_A11	/* GPL0 A11[MPC] */	  \
+			 | MAMR_RLFA_1X		/* Read loop 1 time */	  \
+			 | MAMR_WLFA_1X		/* Write loop 1 time */	  \
+			 | MAMR_TLFA_4X)	/* Timer loop 4 times */
+
+/* 9 column SDRAM */
+#define SDRAM_MAMR_9COL ((SDRAM_MAMR_8COL & (~MAMR_G0CLA_A11)) | MAMR_G0CLA_A10)
+
+/* base address 0, 32-bit port, SDRAM UPM, valid */
+#define SDRAM_BR_VALUE   (BR_PS_32 | BR_MS_UPMA | BR_V)
+
+/*  up to 256MB, SAM, G5LS - will be adjusted for actual size */
+#define SDRAM_OR_PRELIM  (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
+
+/* This is the Mode Select Register value for the SDRAM.
+ * Burst length: 4
+ * Burst Type: sequential
+ * CAS Latency: 2
+ * Write Burst Length: burst
+ */
+#define SDRAM_MODE   0x22	/* CAS latency 2, burst length 4 */
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram(int board_type)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	uint size_sdram = 0;
+	uint size_sdram9 = 0;
+	uint base = 0;		/* SDRAM must start at 0 */
+	int i;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Configure the refresh (mostly).  This needs to be
+	 * based upon processor clock speed and optimized to provide
+	 * the highest level of performance.
+	 *
+	 * Preliminary prescaler for refresh.
+	 * This value is selected for four cycles in 31.2 us,
+	 * which gives 8192 cycles in 64 milliseconds.
+	 * This may be too fast, but works for any memory.
+	 * It is adjusted to 4096 cycles in 64 milliseconds if
+	 * possible once we know what memory we have.
+         *
+	 * We have to be careful changing UPM registers after we
+	 * ask it to run these commands.
+	 *
+	 * PTA - periodic timer period for our design is
+	 *       50 MHz x 31.2us
+	 *       ---------------  = 195
+	 *       1 x 8 x 1
+	 *
+	 *    50MHz clock
+	 *    31.2us refresh interval
+	 *    SCCR[DFBRG] 0
+	 *    PTP divide by 8
+	 *    1 chip select
+         */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;	/* 0x0800 */
+	memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
+
+	/* The SDRAM Mode Register value is shifted left 2 bits since
+	 * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
+	 */
+	memctl->memc_mar = SDRAM_MODE << 2;	/* MRS code */
+	udelay(200);		/* SDRAM needs 200uS before set it up */
+
+	/* Now run the precharge/nop/mrs commands. */
+	memctl->memc_mcr = SDRAM_MCR_PRE;
+	udelay(2);
+
+	/* Run 8 refresh cycles (2 sets of 4) */
+	memctl->memc_mcr = SDRAM_MCR_REFR;	/* run refresh twice */
+	udelay(2);
+
+	/* some brands want Mode Register set after the refresh
+	 * cycles. This shouldn't hurt anything for the brands
+	 * that were happy with the first time we set it.
+	 */
+	memctl->memc_mcr = SDRAM_MCR_MRS;
+	udelay(2);
+
+	memctl->memc_mamr = SDRAM_MAMR_8COL;	/* enable refresh */
+	memctl->memc_or3 = SDRAM_OR_PRELIM;
+	memctl->memc_br3 = SDRAM_BR_VALUE + base;
+
+	/* Some brands need at least 10 DRAM accesses to stabilize.
+	 * It wont hurt the brands that don't.
+	 */
+	for (i=0; i<10; ++i) {
+		volatile ulong *addr = (volatile ulong *)base;
+		ulong val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/* Check SDRAM memory Size in 8 column mode.
+	 * For a 9 column memory we will get half the actual size.
+	 */
+	size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
+
+	/* Check SDRAM memory Size in 9 column mode.
+	 * For an 8 column memory we will see at most 4 megabytes.
+	 */
+	memctl->memc_mamr = SDRAM_MAMR_9COL;
+	size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
+
+	if (size_sdram < size_sdram9)	/* leave configuration at 9 columns */
+		size_sdram = size_sdram9;
+	else				/* go back to 8 columns */
+		memctl->memc_mamr = SDRAM_MAMR_8COL;
+
+	/* adjust or3 for actual size of SDRAM
+	 */
+	memctl->memc_or3 |= ORMASK(size_sdram);
+
+	/* Adjust refresh rate depending on SDRAM type.
+	 * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
+	 * it at the current (fast) rate.
+	 * For 16, 64 and 128 MBit half the rate will do.
+	 */
+	if (size_sdram <= 32 * 1024 * 1024)
+		memctl->memc_mptpr = MPTPR_PTP_DIV16;	/* 0x0400 */
+
+	return (size_sdram);
+}
+

cpu/mpc8xx/start.S

+/*
+ *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
+ *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*  U-Boot - Startup Code for PowerPC based Embedded Boards
+ *
+ *
+ *  The processor starts at 0x00000100 and the code is executed
+ *  from flash. The code is organized to be at an other address
+ *  in memory, but as long we don't jump around before relocating.
+ *  board_init lies at a quite high address and when the cpu has
+ *  jumped there, everything is ok.
+ *  This works because the cpu gives the FLASH (CS0) the whole
+ *  address space at startup, and board_init lies as a echo of
+ *  the flash somewhere up there in the memorymap.
+ *
+ *  board_init will change CS0 to be positioned at the correct
+ *  address and (s)dram will be positioned at address 0
+ */
+#include <config.h>
+#include <mpc8xx.h>
+#include <version.h>
+
+#define CONFIG_8xx 1		/* needed for Linux kernel header files */
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef  CONFIG_IDENT_STRING
+#define  CONFIG_IDENT_STRING ""
+#endif
+
+/* We don't want the  MMU yet.
+*/
+#undef	MSR_KERNEL
+#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r14 to access the GOT
+ */
+	START_GOT
+	GOT_ENTRY(_GOT2_TABLE_)
+	GOT_ENTRY(_FIXUP_TABLE_)
+
+	GOT_ENTRY(_start)
+	GOT_ENTRY(_start_of_vectors)
+	GOT_ENTRY(_end_of_vectors)
+	GOT_ENTRY(transfer_to_handler)
+
+	GOT_ENTRY(_end)
+	GOT_ENTRY(.bss)
+#if defined(CONFIG_FADS) || defined(CONFIG_ICU862)
+	GOT_ENTRY(environment)
+#endif
+	END_GOT
+
+/*
+ * r3 - 1st arg to board_init(): IMMP pointer
+ * r4 - 2nd arg to board_init(): boot flag
+ */
+	.text
+	.long	0x27051956		/* U-Boot Magic Number			*/
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION
+	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii CONFIG_IDENT_STRING, "\0"
+
+	. = EXC_OFF_SYS_RESET
+	.globl	_start
+_start:
+	lis	r3, CFG_IMMR@h		/* position IMMR */
+	mtspr	638, r3
+	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH	*/
+	b	boot_cold
+
+	. = EXC_OFF_SYS_RESET + 0x10
+
+	.globl	_start_warm
+_start_warm:
+	li	r21, BOOTFLAG_WARM	/* Software reboot			*/
+	b	boot_warm
+
+boot_cold:
+boot_warm:
+
+	/* Initialize machine status; enable machine check interrupt		*/
+	/*----------------------------------------------------------------------*/
+	li	r3, MSR_KERNEL		/* Set ME, RI flags */
+	mtmsr	r3
+	mtspr	SRR1, r3		/* Make SRR1 match MSR */
+
+	mfspr	r3, ICR			/* clear Interrupt Cause Register */
+
+	/* Initialize debug port registers					*/
+	/*----------------------------------------------------------------------*/
+	xor	r0, r0, r0		/* Clear R0 */
+	mtspr	LCTRL1, r0		/* Initialize debug port regs */
+	mtspr	LCTRL2, r0
+	mtspr	COUNTA, r0
+	mtspr	COUNTB, r0
+
+	/* Reset the caches							*/
+	/*----------------------------------------------------------------------*/
+
+	mfspr	r3, IC_CST		/* Clear error bits */
+	mfspr	r3, DC_CST
+
+	lis	r3, IDC_UNALL@h		/* Unlock all */
+	mtspr	IC_CST, r3
+	mtspr	DC_CST, r3
+
+	lis	r3, IDC_INVALL@h	/* Invalidate all */
+	mtspr	IC_CST, r3
+	mtspr	DC_CST, r3
+
+	lis	r3, IDC_DISABLE@h	/* Disable data cache */
+	mtspr	DC_CST, r3
+
+#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
+					/* On IP860 and PCU E,
+					 * we cannot enable IC yet
+					 */
+	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
+#endif
+	mtspr	IC_CST, r3
+
+	/* invalidate all tlb's							*/
+	/*----------------------------------------------------------------------*/
+
+	tlbia
+	isync
+
+	/*
+	 * Calculate absolute address in FLASH and jump there
+	 *----------------------------------------------------------------------*/
+
+	lis	r3, CFG_MONITOR_BASE@h
+	ori	r3, r3, CFG_MONITOR_BASE@l
+	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+	mtlr	r3
+	blr
+
+in_flash:
+
+	/* initialize some SPRs that are hard to access from C			*/
+	/*----------------------------------------------------------------------*/
+
+	lis	r3, CFG_IMMR@h		/* pass IMMR as arg1 to C routine */
+	ori	r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
+	/* Note: R0 is still 0 here */
+	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
+	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
+
+	/*
+	 * Disable serialized ifetch and show cycles
+	 * (i.e. set processor to normal mode).
+	 * This is also a silicon bug workaround, see errata
+	 */
+
+	li	r2, 0x0007
+	mtspr	ICTRL, r2
+
+	/* Set up debug mode entry */
+
+	lis	r2, CFG_DER@h
+	ori	r2, r2, CFG_DER@l
+	mtspr	DER, r2
+
+	/* let the C-code set up the rest					*/
+	/*									*/
+	/* Be careful to keep code relocatable !				*/
+	/*----------------------------------------------------------------------*/
+
+	GET_GOT			/* initialize GOT access			*/
+
+	/* r3: IMMR */
+	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
+
+	mr	r3, r21
+	/* r3: BOOTFLAG */
+	bl	board_init_f	/* run 1st part of board init code (from Flash) */
+
+
+
+	.globl	_start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception.  "Never" generated on the 860. */
+	STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception.  "Never" generated on the 860. */
+	STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+
+/* Alignment exception. */
+	. = 0x600
+Alignment:
+	EXCEPTION_PROLOG
+	mfspr	r4,DAR
+	stw	r4,_DAR(r21)
+	mfspr	r5,DSISR
+	stw	r5,_DSISR(r21)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	li	r20,MSR_KERNEL
+	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+	lwz	r6,GOT(transfer_to_handler)
+	mtlr	r6
+	blrl
+.L_Alignment:
+	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
+	.long	int_return - _start + EXC_OFF_SYS_RESET
+
+/* Program check exception */
+	. = 0x700
+ProgramCheck:
+	EXCEPTION_PROLOG
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	li	r20,MSR_KERNEL
+	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+	lwz	r6,GOT(transfer_to_handler)
+	mtlr	r6
+	blrl
+.L_ProgramCheck:
+	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
+	.long	int_return - _start + EXC_OFF_SYS_RESET
+
+	/* No FPU on MPC8xx.  This exception is not supposed to happen.
+	*/
+	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+	/* I guess we could implement decrementer, and may have
+	 * to someday for timekeeping.
+	 */
+	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+
+	. = 0xc00
+/*
+ * r0 - SYSCALL number
+ * r3-... arguments
+ */
+SystemCall:
+	addis	r11,r0,0		/* get functions table addr */
+	ori	r11,r11,0		/* Note: this code is patched in trap_init */
+	addis	r12,r0,0		/* get number of functions */
+	ori	r12,r12,0
+
+	cmplw	0, r0, r12
+	bge	1f
+
+	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
+	add	r11,r11,r0
+	lwz	r11,0(r11)
+
+	li	r12,0xd00-4*3		/* save LR & SRRx */
+	mflr	r0
+	stw	r0,0(r12)
+	mfspr	r0,SRR0
+	stw	r0,4(r12)
+	mfspr	r0,SRR1
+	stw	r0,8(r12)
+
+	li	r12,0xc00+_back-SystemCall
+	mtlr	r12
+	mtspr	SRR0,r11
+
+1:	SYNC
+	rfi
+
+_back:
+
+	mfmsr	r11			/* Disable interrupts */
+	li	r12,0
+	ori	r12,r12,MSR_EE
+	andc	r11,r11,r12
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r11
+	SYNC
+
+	li	r12,0xd00-4*3		/* restore regs */
+	lwz	r11,0(r12)
+	mtlr	r11
+	lwz	r11,4(r12)
+	mtspr	SRR0,r11
+	lwz	r11,8(r12)
+	mtspr	SRR1,r11
+
+	SYNC
+	rfi
+
+	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+
+	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+
+	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
+	 * for all unimplemented and illegal instructions.
+	 */
+	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
+
+	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
+	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
+
+	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
+	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
+	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
+	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
+	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
+	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
+	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
+
+	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
+	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
+	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
+	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
+
+
+	.globl	_end_of_vectors
+_end_of_vectors:
+
+
+	. = 0x2000
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+	.globl	transfer_to_handler
+transfer_to_handler:
+	stw	r22,_NIP(r21)
+	lis	r22,MSR_POW@h
+	andc	r23,r23,r22
+	stw	r23,_MSR(r21)
+	SAVE_GPR(7, r21)
+	SAVE_4GPRS(8, r21)
+	SAVE_8GPRS(12, r21)
+	SAVE_8GPRS(24, r21)
+	mflr	r23
+	andi.	r24,r23,0x3f00		/* get vector offset */
+	stw	r24,TRAP(r21)
+	li	r22,0
+	stw	r22,RESULT(r21)
+	mtspr	SPRG2,r22		/* r1 is now kernel sp */
+	lwz	r24,0(r23)		/* virtual address of handler */
+	lwz	r23,4(r23)		/* where to go when done */
+	mtspr	SRR0,r24
+	mtspr	SRR1,r20
+	mtlr	r23
+	SYNC
+	rfi				/* jump to handler, enable MMU */
+
+int_return:
+	mfmsr	r28			/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)		/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	SRR0,r2
+	mtspr	SRR1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfi
+
+/* Cache functions.
+*/
+	.globl	icache_enable
+icache_enable:
+	SYNC
+	lis	r3, IDC_INVALL@h
+	mtspr	IC_CST, r3
+	lis	r3, IDC_ENABLE@h
+	mtspr	IC_CST, r3
+	blr
+
+	.globl	icache_disable
+icache_disable:
+	SYNC
+	lis	r3, IDC_DISABLE@h
+	mtspr	IC_CST, r3
+	blr
+
+	.globl	icache_status
+icache_status:
+	mfspr	r3, IC_CST
+	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	blr
+
+	.globl	dcache_enable
+dcache_enable:
+#if 0
+	SYNC
+#endif
+#if 1
+	lis	r3, 0x0400		/* Set cache mode with MMU off */
+	mtspr	MD_CTR, r3
+#endif
+
+	lis	r3, IDC_INVALL@h
+	mtspr	DC_CST, r3
+#if 0
+	lis	r3, DC_SFWT@h
+	mtspr	DC_CST, r3
+#endif
+	lis	r3, IDC_ENABLE@h
+	mtspr	DC_CST, r3
+	blr
+
+	.globl	dcache_disable
+dcache_disable:
+	SYNC
+	lis	r3, IDC_DISABLE@h
+	mtspr	DC_CST, r3
+	lis	r3, IDC_INVALL@h
+	mtspr	DC_CST, r3
+	blr
+
+	.globl	dcache_status
+dcache_status:
+	mfspr	r3, DC_CST
+	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	blr
+
+	.globl	dc_read
+dc_read:
+	mtspr	DC_ADR, r3
+	mfspr	r3, DC_DAT
+	blr
+
+/*
+ * unsigned int get_immr (unsigned int mask)
+ *
+ * return (mask ? (IMMR & mask) : IMMR);
+ */
+	.globl	get_immr
+get_immr:
+	mr	r4,r3		/* save mask */
+	mfspr	r3, IMMR	/* IMMR */
+	cmpwi	0,r4,0		/* mask != 0 ? */
+	beq	4f
+	and	r3,r3,r4	/* IMMR & mask */
+4:
+	blr
+
+	.globl get_pvr
+get_pvr:
+	mfspr	r3, PVR
+	blr
+
+
+	.globl wr_ic_cst
+wr_ic_cst:
+	mtspr	IC_CST, r3
+	blr
+
+	.globl rd_ic_cst
+rd_ic_cst:
+	mfspr	r3, IC_CST
+	blr
+
+	.globl wr_ic_adr
+wr_ic_adr:
+	mtspr	IC_ADR, r3
+	blr
+
+
+	.globl wr_dc_cst
+wr_dc_cst:
+	mtspr	DC_CST, r3
+	blr
+
+	.globl rd_dc_cst
+rd_dc_cst:
+	mfspr	r3, DC_CST
+	blr
+
+	.globl wr_dc_adr
+wr_dc_adr:
+	mtspr	DC_ADR, r3
+	blr
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	mr	r1,  r3		/* Set new stack pointer		*/
+	mr	r9,  r4		/* Save copy of Global Data pointer	*/
+	mr	r10, r5		/* Save copy of Destination Address	*/
+
+	mr	r3,  r5				/* Destination Address	*/
+	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
+	ori	r4, r4, CFG_MONITOR_BASE@l
+	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
+	ori	r5, r5, CFG_MONITOR_LEN@l
+	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
+
+	/*
+	 * Fix GOT pointer:
+	 *
+	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+	 *
+	 * Offset:
+	 */
+	sub	r15, r10, r4
+
+	/* First our own GOT */
+	add	r14, r14, r15
+	/* the the one used by the C code */
+	add	r30, r30, r15
+
+	/*
+	 * Now relocate code
+	 */
+
+	cmplw	cr1,r3,r4
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	beq	cr1,4f		/* In place copy is not necessary	*/
+	beq	7f		/* Protect against 0 count		*/
+	mtctr	r0
+	bge	cr1,2f
+
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+1:	lwzu	r0,4(r8)
+	stwu	r0,4(r7)
+	bdnz	1b
+	b	4f
+
+2:	slwi	r0,r0,2
+	add	r8,r4,r0
+	add	r7,r3,r0
+3:	lwzu	r0,-4(r8)
+	stwu	r0,-4(r7)
+	bdnz	3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:	cmpwi	r6,0
+	add	r5,r3,r5
+	beq	7f		/* Always flush prefetch queue in any case */
+	subi	r0,r6,1
+	andc	r3,r3,r0
+	mr	r4,r3
+5:	dcbst	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	5b
+	sync			/* Wait for all dcbst to complete on bus */
+	mr	r4,r3
+6:	icbi	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	6b
+7:	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+	mtlr	r0
+	blr
+
+in_ram:
+
+	/*
+	 * Relocation Function, r14 point to got2+0x8000
+	 *
+         * Adjust got2 pointers, no need to check for 0, this code
+         * already puts a few entries in the table.
+	 */
+	li	r0,__got2_entries@sectoff@l
+	la	r3,GOT(_GOT2_TABLE_)
+	lwz	r11,GOT(_GOT2_TABLE_)
+	mtctr	r0
+	sub	r11,r3,r11
+	addi	r3,r3,-4
+1:	lwzu	r0,4(r3)
+	add	r0,r0,r11
+	stw	r0,0(r3)
+	bdnz	1b
+
+	/*
+         * Now adjust the fixups and the pointers to the fixups
+	 * in case we need to move ourselves again.
+	 */
+2:	li	r0,__fixup_entries@sectoff@l
+	lwz	r3,GOT(_FIXUP_TABLE_)
+	cmpwi	r0,0
+	mtctr	r0
+	addi	r3,r3,-4
+	beq	4f
+3:	lwzu	r4,4(r3)
+	lwzux	r0,r4,r11
+	add	r0,r0,r11
+	stw	r10,0(r3)
+	stw	r0,0(r4)
+	bdnz	3b
+4:
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	lwz	r3,GOT(.bss)
+#if defined(CONFIG_FADS) || defined(CONFIG_ICU862)
+	/*
+	 * For the FADS - the environment is the very last item in flash.
+	 * The real .bss stops just before environment starts, so only
+	 * clear up to that point.
+	 */
+	lwz	r4,GOT(environment)
+#else
+	lwz	r4,GOT(_end)
+#endif
+
+	cmplw	0, r3, r4
+	beq	6f
+
+	li	r0, 0
+5:
+	stw	r0, 0(r3)
+	addi	r3, r3, 4
+	cmplw	0, r3, r4
+	bne	5b
+6:
+
+	mr	r3, r9		/* Global Data pointer		*/
+	mr	r4, r10		/* Destination Address		*/
+	bl	board_init_r
+
+	/* Problems accessing "end" in C, so do it here */
+	.globl	get_endaddr
+get_endaddr:
+	lwz	r3,GOT(_end)
+	blr
+
+	/*
+	 * Copy exception vector code to low memory
+	 *
+	 * r3: dest_addr
+	 * r7: source address, r8: end address, r9: target address
+	 */
+	.globl	trap_init
+trap_init:
+	lwz	r7, GOT(_start)
+	lwz	r8, GOT(_end_of_vectors)
+
+	rlwinm	r9, r7, 0, 22, 31	/* _start & 0x3FF	*/
+
+	cmplw	0, r7, r8
+	bgelr				/* return if r7>=r8 - just in case */
+
+	mflr	r4			/* save link register		*/
+1:
+	lwz	r0, 0(r7)
+	stw	r0, 0(r9)
+	addi	r7, r7, 4
+	addi	r9, r9, 4
+	cmplw	0, r7, r8
+	bne	1b
+
+	/*
+	 * relocate `hdlr' and `int_return' entries
+	 */
+	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	2b
+
+	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	3b
+
+	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	4b
+
+	mtlr	r4			/* restore link register	*/
+	blr
+
+	/*
+	 * Function: relocate entries for one exception vector
+	 */
+trap_reloc:
+	lwz	r0, 0(r7)		/* hdlr ...			*/
+	add	r0, r0, r3		/*  ... += dest_addr		*/
+	stw	r0, 0(r7)
+
+	lwz	r0, 4(r7)		/* int_return ...		*/
+	add	r0, r0, r3		/*  ... += dest_addr		*/
+	stw	r0, 4(r7)
+
+	sync
+	isync
+
+	blr

doc/README.IPHASE4539

+
+This file contains basic information on the port of U-Boot to IPHASE4539
+(Interphase 4539 T1/E1/J1 PMC Communications Controller).
+All the changes fit in the common U-Boot infrastructure, providing a new
+IPHASE4539-specific entry in makefiles. To build U-Boot for IPHASE4539,
+type "make IPHASE4539_config", edit the "include/config_IPHASE4539.h"
+file if necessary, then type "make".
+
+
+Common file modifications:
+--------------------------
+
+The following common files have been modified by this project:
+(starting from the ppcboot-1.1.5/ directory)
+
+MAKEALL				- IPHASE4539 entry added
+Makefile			- IPHASE4539_config entry added
+
+
+New files:
+----------
+
+The following new files have been added by this project:
+(starting from the ppcboot-1.1.5/ directory)
+
+board/iphase4539/		- board-specific directory
+board/iphase4539/Makefile	- board-specific makefile
+board/iphase4539/config.mk	- config file
+board/iphase4539/flash.c	- flash driver (for AM29LV033C)
+board/iphase4539/ppcboot.lds	- linker script
+board/iphase4539/iphase4539.c	- ioport and memory initialization
+include/config_IPHASE4539.h	- main configuration file
+
+
+New configuration options:
+--------------------------
+
+CONFIG_IPHASE4539
+
+	Main board-specific option (should be defined for IPHASE4539).
+
+
+Acceptance criteria tests:
+--------------------------
+
+The following tests have been conducted to validate the port of U-Boot
+to IPHASE4539:
+
+1. Operation on serial console:
+
+With SMC1 defined as console in the main configuration file, the U-Boot
+output appeared on the serial terminal connected to the 2.5mm stereo jack
+connector as follows:
+
+------------------------------------------------------------------------------
+=> help
+autoscr - run script from memory
+base    - print or set address offset
+bdinfo  - print Board Info structure
+bootm   - boot application image from memory
+bootp   - boot image via network using BootP/TFTP protocol
+bootd   - boot default, i.e., run 'bootcmd'
+cmp     - memory compare
+coninfo - print console devices and informations
+cp      - memory copy
+crc32   - checksum calculation
+dcache  - enable or disable data cache
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+icache  - enable or disable instruction cache
+iminfo  - print header information for application image
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loop    - infinite loop on address range
+md      - memory display
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nm      - memory modify (constant address)
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+tftpboot- boot image via network using TFTP protocol
+               and env variables ipaddr and serverip
+version - print monitor version
+?       - alias for 'help'
+=>
+------------------------------------------------------------------------------
+
+
+2. Flash driver operation
+
+The following sequence was performed to test the "flinfo" command:
+
+------------------------------------------------------------------------------
+=> flinfo
+
+Bank # 1: AMD AM29LV033C (32 Mbit, uniform sectors)
+  Size: 4 MB in 64 Sectors
+  Sector Start Addresses:
+    FF800000 (RO) FF810000 (RO) FF820000      FF830000      FF840000
+    FF850000      FF860000      FF870000      FF880000      FF890000
+    FF8A0000      FF8B0000      FF8C0000      FF8D0000      FF8E0000
+    FF8F0000      FF900000      FF910000      FF920000      FF930000
+    FF940000      FF950000      FF960000      FF970000      FF980000
+    FF990000      FF9A0000      FF9B0000      FF9C0000      FF9D0000
+    FF9E0000      FF9F0000      FFA00000      FFA10000      FFA20000
+    FFA30000      FFA40000      FFA50000      FFA60000      FFA70000
+    FFA80000      FFA90000      FFAA0000      FFAB0000      FFAC0000
+    FFAD0000      FFAE0000      FFAF0000      FFB00000 (RO) FFB10000 (RO)
+    FFB20000 (RO) FFB30000 (RO) FFB40000      FFB50000      FFB60000
+    FFB70000      FFB80000      FFB90000      FFBA0000      FFBB0000
+    FFBC0000      FFBD0000      FFBE0000      FFBF0000
+------------------------------------------------------------------------------
+
+Note: the Hardware Configuration Word (HWC) of the 8260 is on the
+first sector of the flash and should not be touched. The U-Boot
+environment variables are stored on second sector and U-Boot
+starts at the address 0xFFB00000.
+
+
+The following sequence was performed to test the erase command:
+
+------------------------------------------------------------------------------
+=> cp 0 ff880000 10
+Copy to Flash... done
+=> md ff880000 20
+ff880000: ff000000 60000000 60000000 7c7f1b78    ....`...`...|..x
+ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78    |.#x|.+x|.3x|.;x
+ff880020: 3b000000 4811e0f5 48003719 480036a5    ;...H...H.7.H.6.
+ff880030: 480036f9 48003731 48005c5d 7c7a1b78    H.6.H.71H.\]|z.x
+ff880040: ffffffff ffffffff ffffffff ffffffff    ................
+ff880050: ffffffff ffffffff ffffffff ffffffff    ................
+ff880060: ffffffff ffffffff ffffffff ffffffff    ................
+ff880070: ffffffff ffffffff ffffffff ffffffff    ................
+=> erase ff880000 ff88ffff
+Erase Flash from 0xff880000 to 0xff88ffff
+.. done
+Erased 1 sectors
+=> md ff880000
+ff880000: ffffffff ffffffff ffffffff ffffffff    ................
+ff880010: ffffffff ffffffff ffffffff ffffffff    ................
+ff880020: ffffffff ffffffff ffffffff ffffffff    ................
+ff880030: ffffffff ffffffff ffffffff ffffffff    ................
+ff880040: ffffffff ffffffff ffffffff ffffffff    ................
+ff880050: ffffffff ffffffff ffffffff ffffffff    ................
+ff880060: ffffffff ffffffff ffffffff ffffffff    ................
+ff880070: ffffffff ffffffff ffffffff ffffffff    ................
+=> cp 0 ff880000 10
+Copy to Flash... done
+=> md ff880000 20
+ff880000: ff000000 60000000 60000000 7c7f1b78    ....`...`...|..x
+ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78    |.#x|.+x|.3x|.;x
+ff880020: 3b000000 4811e0f5 48003719 480036a5    ;...H...H.7.H.6.
+ff880030: 480036f9 48003731 48005c5d 7c7a1b78    H.6.H.71H.\]|z.x
+ff880040: ffffffff ffffffff ffffffff ffffffff    ................
+ff880050: ffffffff ffffffff ffffffff ffffffff    ................
+ff880060: ffffffff ffffffff ffffffff ffffffff    ................
+ff880070: ffffffff ffffffff ffffffff ffffffff    ................
+=> erase 1:8
+Erase Flash Sectors 8-8 in Bank # 1
+.. done
+=> md ff880000 20
+ff880000: ffffffff ffffffff ffffffff ffffffff    ................
+ff880010: ffffffff ffffffff ffffffff ffffffff    ................
+ff880020: ffffffff ffffffff ffffffff ffffffff    ................
+ff880030: ffffffff ffffffff ffffffff ffffffff    ................
+ff880040: ffffffff ffffffff ffffffff ffffffff    ................
+ff880050: ffffffff ffffffff ffffffff ffffffff    ................
+ff880060: ffffffff ffffffff ffffffff ffffffff    ................
+ff880070: ffffffff ffffffff ffffffff ffffffff    ................
+=> cp 0 ff880000 10
+Copy to Flash... done
+=> cp 0 ff890000 10
+=> md ff880000 20
+ff880000: ff000000 60000000 60000000 7c7f1b78    ....`...`...|..x
+ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78    |.#x|.+x|.3x|.;x
+ff880020: 3b000000 4811e0f5 48003719 480036a5    ;...H...H.7.H.6.
+ff880030: 480036f9 48003731 48005c5d 7c7a1b78    H.6.H.71H.\]|z.x
+ff880040: ffffffff ffffffff ffffffff ffffffff    ................
+ff880050: ffffffff ffffffff ffffffff ffffffff    ................
+ff880060: ffffffff ffffffff ffffffff ffffffff    ................
+ff880070: ffffffff ffffffff ffffffff ffffffff    ................
+=> md ff890000
+ff890000: ff000000 60000000 60000000 7c7f1b78    ....`...`...|..x
+ff890010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78    |.#x|.+x|.3x|.;x
+ff890020: 3b000000 4811e0f5 48003719 480036a5    ;...H...H.7.H.6.
+ff890030: 480036f9 48003731 48005c5d 7c7a1b78    H.6.H.71H.\]|z.x
+ff890040: ffffffff ffffffff ffffffff ffffffff    ................
+ff890050: ffffffff ffffffff ffffffff ffffffff    ................
+ff890060: ffffffff ffffffff ffffffff ffffffff    ................
+ff890070: ffffffff ffffffff ffffffff ffffffff    ................
+=> erase 1:8-9
+Erase Flash Sectors 8-9 in Bank # 1
+.... done
+=> md ff880000 20
+ff880000: ffffffff ffffffff ffffffff ffffffff    ................
+ff880010: ffffffff ffffffff ffffffff ffffffff    ................
+ff880020: ffffffff ffffffff ffffffff ffffffff    ................
+ff880030: ffffffff ffffffff ffffffff ffffffff    ................
+ff880040: ffffffff ffffffff ffffffff ffffffff    ................
+ff880050: ffffffff ffffffff ffffffff ffffffff    ................
+ff880060: ffffffff ffffffff ffffffff ffffffff    ................
+ff880070: ffffffff ffffffff ffffffff ffffffff    ................
+=> md ff890000
+ff890000: ffffffff ffffffff ffffffff ffffffff    ................
+ff890010: ffffffff ffffffff ffffffff ffffffff    ................
+ff890020: ffffffff ffffffff ffffffff ffffffff    ................
+ff890030: ffffffff ffffffff ffffffff ffffffff    ................
+ff890040: ffffffff ffffffff ffffffff ffffffff    ................
+ff890050: ffffffff ffffffff ffffffff ffffffff    ................
+ff890060: ffffffff ffffffff ffffffff ffffffff    ................
+ff890070: ffffffff ffffffff ffffffff ffffffff    ................
+=>
+------------------------------------------------------------------------------
+
+
+The following sequence was performed to test the Flash programming commands:
+
+------------------------------------------------------------------------------
+=> erase ff880000 ff88ffff
+Erase Flash from 0xff880000 to 0xff88ffff
+.. done
+Erased 1 sectors
+=> cp 0 ff880000 10
+Copy to Flash... done
+=> md 0 20
+00000000: ff000000 60000000 60000000 7c7f1b78    ....`...`...|..x
+00000010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78    |.#x|.+x|.3x|.;x
+00000020: 3b000000 4811e0f5 48003719 480036a5    ;...H...H.7.H.6.
+00000030: 480036f9 48003731 48005c5d 7c7a1b78    H.6.H.71H.\]|z.x
+00000040: 3c83c000 2c040000 40823378 7c0000a6    <...,...@.3x|...
+00000050: 60000030 7c1b03a6 3c00c000 600035ec    `..0|...<...`.5.
+00000060: 7c1a03a6 4c000064 00000000 00000000    |...L..d........
+00000070: 00000000 00000000 00000000 00000000    ................
+=> md ff880000 20
+ff880000: ff000000 60000000 60000000 7c7f1b78    ....`...`...|..x
+ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78    |.#x|.+x|.3x|.;x
+ff880020: 3b000000 4811e0f5 48003719 480036a5    ;...H...H.7.H.6.
+ff880030: 480036f9 48003731 48005c5d 7c7a1b78    H.6.H.71H.\]|z.x
+ff880040: ffffffff ffffffff ffffffff ffffffff    ................
+ff880050: ffffffff ffffffff ffffffff ffffffff    ................
+ff880060: ffffffff ffffffff ffffffff ffffffff    ................
+ff880070: ffffffff ffffffff ffffffff ffffffff    ................
+=>
+------------------------------------------------------------------------------
+
+
+The following sequence was performed to test storage of the environment
+variables in Flash:
+
+------------------------------------------------------------------------------
+=> setenv foo bar
+=> saveenv
+Un-Protected 1 sectors
+Erasing Flash...
+.. done
+Erased 1 sectors
+Saving Environment to Flash...
+Protected 1 sectors
+=> reset
+...
+=> printenv
+...
+foo=bar
+...
+Environment size: 339/65532 bytes
+=>
+------------------------------------------------------------------------------
+
+
+The following sequence was performed to test image download and run over
+Ethernet interface (both interfaces were tested):
+
+------------------------------------------------------------------------------
+=> tftpboot 40000 hello_world.bin
+ARP broadcast 1
+TFTP from server 10.0.0.1; our IP address is 10.0.0.8
+Filename 'hello_world.bin'.
+Load address: 0x40000
+Loading: #############
+done
+Bytes transferred = 65932 (1018c hex)
+=> go 40004
+## Starting application at 0x00040004 ...
+Hello World
+argc = 1
+argv[0] = "40004"
+argv[1] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+=>
+------------------------------------------------------------------------------
+
+
+3. Known Problems
+
+None for the moment.
+
+
+----------------------------------------------------------------------------
+U-Boot and Linux for Interphase 4539 T1/E1/J1 PMC Communications Controller
+----------------------------------------------------------------------------
+
+U-Boot:
+
+	Configure and make U-Boot:
+
+	$ cd <path>/u-boot
+	$ make IPHASE4539_config
+	$ make dep
+	$ make
+	$ cp -p u-boot.bin /tftpboot
+
+	Load u-boot.bin into the Flash memory at 0xffb00000.
+
+
+Linux:
+
+	Configure and make Linux:
+
+	$ cd <patch>/linux-2.4
+	$ make IPHASE4539_config
+	$ make oldconfig
+	$ make dep
+	$ make pImage
+	$ cp -p arch/ppc/mbxboot/pImage /tftpboot
+
+	Load pImage via tftp and boot it.
+
+
+Flash organisation:
+
+	The following preliminary layout of the Flash memory
+	is defined:
+
+	0xff800000 (   0    -   64 kB): Hardware Configuration Word.
+	0xff810000 (  64 kB -  128 kB): U-Boot Environment.
+	0xff820000 ( 128 kB -    3 MB): RAMdisk.
+	0xffb00000 (   3 MB - 3328 kB): U-Boot.
+	0xffb40000 (3328 KB -    4 MB): Linux Kernel.
+
+
+For further information concerning U-Boot and Linux please consult
+the "DENX U-Boot and Linux Guide".
+
+
+(C) 2002 Wolfgang Grandegger, DENX Software Engineering, wg@denx.de
+===================================================================

doc/README.RPXClassic

+# Porting U-Boot onto RPXClassic LF_BW31 board
+# Written by Pierre AUBERT
+# E-Mail  p.aubert@staubli.com
+# Stubli Faverges - <www.staubli.com>
+#
+# Sept. 20 2001
+#
+# Cross compile: Montavista Hardhat ported on HP-UX 10.20
+#
+
+Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000
+DRAM : 16 Mb from 0
+NVRAM : 512 kb from 0xfa000000
+
+
+- environment is stored in NVRAM
+- Mac address is read from EEPROM
+- ethernet on SCC1 or fast ethernet on FEC are running (depending on the
+  configuration flag CONFIG_FEC_ENET)
+
+

doc/README.fads

+/*
+ * (C) Copyright 2000
+ * Dave Ellis, SIXNET, dge@sixnetio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+Using the Motorola MPC8XXFADS development board
+===============================================
+
+CONFIGURATIONS
+--------------
+
+There are ready-to-use default configurations available for the
+FADS823, FADS850SAR and FADS860T. The FADS860T configuration also
+works for the 855T processor.
+
+LOADING U-Boot INTO FADS FLASH MEMORY
+--------------------------------------
+
+MPC8BUG can load U-Boot into the FLASH memory using LOADF.
+
+    loadf u-boot.srec 100000
+
+
+STARTING U-Boot FROM MPC8BUG
+-----------------------------
+
+To start U-Boot from MPC8BUG:
+
+1. Reset the board:
+    reset :h
+
+2. Change BR0 and OR0 back to their values at reset:
+    rms memc br0 00000001
+    rms memc or0 00000d34
+
+3. Modify DER so MPC8BUG gets control only when it should:
+    rms der 2002000f
+
+4. Start as if from reset:
+    go 100
+
+This is NOT exactly the same as starting U-Boot without
+MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset.
+After it does the reset it writes SYPCR (to disable the watchdog)
+and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots
+of other initialization). That is why it is necessary to set BR0
+and OR0 to map the FLASH everywhere. U-Boot can't turn on the
+watchdog after that, since MPC8BUG has used the only chance to write
+to SYPCR.
+
+Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets
+U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T
+processor (your mileage may vary). It is probably better (and a lot
+easier) just to accept having the watchdog disabled when the debug
+cable is connected.
+
+in MPC8BUG:
+  reset :h
+  rms memc br0 00000001
+  rms memc or0 00000d34
+  rms der 2000f
+  go 100
+
+Now U-Boot is running with the MPC8BUG value for SYPCR. Use the
+U-Boot 'reset' command to reset the board.
+  =>reset
+Next, in MPC8BUG:
+  rms der 2000f
+  go
+
+Now U-Boot is running with the U-Boot value for SYPCR.
+

doc/README.video

+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+U-Boot MPC8xx video controller driver
+======================================
+
+The driver has been tested with the following configurations:
+
+- MPC823FADS with AD7176 on a PAL TV (YCbYCr) 	- arsenio@tin.it
+- GENIETV    with AD7177 on a PAL TV (YCbYCr)	- arsenio@tin.it

include/asm-ppc/u-boot.h

+/*
+ * (C) Copyright 2000 - 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __U_BOOT_H__
+#define __U_BOOT_H__
+
+/*
+ * Board information passed to Linux kernel from U-Boot
+ *
+ * include/asm-ppc/u-boot.h
+ */
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+	unsigned long	bi_immr_base;	/* base of IMMR register */
+#endif
+	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
+	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
+	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
+	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
+#if defined(CONFIG_8260)
+	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
+	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
+	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
+	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
+#endif
+	unsigned long	bi_baudrate;	/* Console Baudrate */
+#if defined(CONFIG_405GP) || \
+    defined(CONFIG_405CR) || \
+    defined(CONFIG_440)   || \
+    defined(CONFIG_405)
+	unsigned char	bi_s_version[4];	/* Version of this structure */
+	unsigned char	bi_r_version[32];	/* Version of the ROM (IBM) */
+	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
+	unsigned int	bi_plb_busfreq;	/* PLB Bus speed, in Hz */
+	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
+	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
+#endif
+#if defined(CONFIG_HYMOD)
+	hymod_conf_t	bi_hymod_conf;	/* hymod configuration information */
+#endif
+#if defined(CONFIG_EVB64260) || defined(CONFIG_PN62)
+	/* second onboard ethernet port */
+	unsigned char   bi_enet1addr[6];
+#endif
+#if defined(CONFIG_EVB64260)
+	/* third onboard ethernet port */
+	unsigned char	bi_enet2addr[6];
+#endif
+#if defined(CONFIG_NX823)
+	unsigned char	bi_sernum[8];
+#endif
+} bd_t;
+
+#endif /* __ASSEMBLY__ */
+#endif	/* __U_BOOT_H__ */

include/configs/FADS823.h

+ /*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T FADS board.  Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/*
+ * 1999-nov-26: The FADS is using the following physical memorymap:
+ *
+ * ff020000 -> ff02ffff : pcmcia     io remapping
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by U-Boot
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * e0000000 -> f3ffffff : pcmcia     memory remapping by m8xx_pcmcia
+ * fe000000 -> fe1fffff : flash      connected to CS0, setup by U-Boot
+ * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
+*/
+
+#define CFG_PCMCIA_IO_ADDR	0xff020000
+#define CFG_PCMCIA_IO_SIZE	0x10000
+#define CFG_PCMCIA_MEM_ADDR	0xe0000000
+#define CFG_PCMCIA_MEM_SIZE	0x10000
+#define CFG_IMMR		0xFF000000
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x02800000
+#define BCSR_ADDR		((uint) 0xff010000)
+#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	CONFIG_ETHADDR		08:00:22:50:70:63	/* Ethernet address */
+#define CONFIG_ENV_OVERWRITE	1	/* Overwrite the environment */
+
+#define CONFIG_VIDEO		1	/* To enable video controller support */
+#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+/*Now included by CFG_CMD_PCMCIA */
+/*#define CONFIG_PCMCIA		1	/ * To enable PCMCIA support */
+
+/* Video related */
+
+#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
+#define CONFIG_VIDEO_ENCODER_AD7176		1	/* Enable this encoder */
+#define CONFIG_VIDEO_ENCODER_AD7176_ADDR	0x54	/* Default on fads */
+#define CONFIG_VIDEO_SIZE			(2*1024*1024)
+/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
+
+/* Wireless 56Khz 4PPM keyboard on SMCx */
+
+/*#define CONFIG_WL_4PPM_KEYBOARD		1 */
+#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/* SMC to use (0 indexed) */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_MPC823		1
+#define CONFIG_MPC823FADS	1
+#define CONFIG_FADS		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+
+/* Set the CPU speed to 50Mhz on the FADS */
+
+#if 0
+#define MPC8XX_FACT	10			/* Multiply by 10		*/
+#define MPC8XX_XIN	5000000			/* 5 MHz in	*/
+#else
+#define MPC8XX_FACT	10			/* Multiply by 10 */
+#define MPC8XX_XIN	5000000			/* 5 MHz in */
+#define CFG_PLPRCR_MF	(MPC8XX_FACT-1) << 20	/* From 0 to 4095 */
+#endif
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#if 1
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+#define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
+#define CONFIG_BOOTARGS		""
+#define CONFIG_BOOTCOMMAND							\
+"bootp ;" 									\
+"setenv bootargs console=tty0 console=ttyS0 " 					\
+"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " 				\
+"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" 	\
+"bootm"
+#else
+#define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
+#endif
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_ALL
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 0 ... 16 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
+ */
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#if 0
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration						11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer  *
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR       (SCCR_TBS     | \
+				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+				SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+#define BCSR_SIZE		((uint)(64 * 1024))
+
+#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
+#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CFG_MAMR		0x13a01114
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
+
+/* values according to the manual */
+
+#define	BCSR0			((uint) (BCSR_ADDR + 00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/* FADS bitvalues by Helmut Buchsbaum
+ * see MPC8xxADS User's Manual for a proper description
+ * of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      (23)
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_EN             ((uint)0x08000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860SAR
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#endif /* CONFIG_MPC860SAR */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_SPEED          ((uint)0x04000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VCCO               ((uint)0x02000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_ON           ((uint)0x00800000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_RST          ((uint)0x00200000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHRST            ((uint)0x00200000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_MODEM_EN           ((uint)0x00100000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC850
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#endif /* CONFIG_MPC850 */
+
+#define CONFIG_DRAM_50MHZ		1
+#define CONFIG_SDRAM_50MHZ
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+/*
+ * MPC8xx CPM Options
+ */
+#define CONFIG_SCC_ENET 1
+#define CONFIG_SCC2_ENET 1
+#undef  CONFIG_FEC_ENET
+#undef  CONFIG_CPM_IIC
+#undef  CONFIG_UCODE_PATCH
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS    1
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#endif
+
+#endif	/* __CONFIG_H */