update from duco/rk312x_20170517 on rockchip -6.0.1_r55 branches

arch/arm/cpu/armv7/rk32xx/lowlevel_init.S

@@ -60,4 +60,68 @@ ENTRY(v7_outer_cache_disable)
 	pop	{r1, r2, r3, pc}
 ENDPROC(v7_outer_cache_disable)
 #endif
+ENTRY(ResetCpu_asm)
+	#LDR 	R2, =0x20040004
+	#LDR 	R1, =0x00000003
+	STR 	R1, [R2,#0]
+	#STR 	R10, [R11,#0]
+   ;//cruReg->CRU_MODE_CON = 0x33330000;    //cpu enter slow mode
+	    #LDR		R8, =0x20000040
+	    #LDR		R9, =0x33330000
+	   STR	R9, [R8,#0]
+	
+	#LDR 	R1, =0xeca8
+	#LDR 	R2, =0x20000104
+	#LDR 	R3, =0x10000000
+	STR 	R5, [R7,#0]
+	STR 	R3, [R4,#0]
+ResetCpu_loop:
+	 B	ResetCpu_loop
+ENDPROC(ResetCpu_asm)
+
+   /*
+    * void relocate_code (addr_sp, gd, addr_moni)
+    *
+    * This "function" does not return, instead it continues in RAM
+    * after relocating the monitor code.
+    *
+    */
+
+ENTRY(ResetCpu_3026)
+     #mov r1,#0
+stop_loop_3026:
+     mov r7,r0
+     ldr r6,  =0x10080030  /* save addr of destination */
+
+     adr r0, ResetCpu_asm
+     mov r1, r6          /* r1 <- scratch for copy_loop */
+     adr r2, ResetCpu_3026    /* r2 <- source end address     */
+
+reset_copy_loop_3026:
+     ldmia   r0!, {r9-r10}       /* copy from source address [r0]    */
+     stmia   r1!, {r9-r10}       /* copy to   target address [r1]    */
+     cmp r0, r2          /* until source end address [r2]    */
+     blo reset_copy_loop_3026
+
+    #LDR 	R2, =0x20020004
+    LDR 	R2, =0x20004004
+     LDR 	R1, =0x00000003
+     #STR 	R1, [R2,#0]
+	
+     LDR 	R3, =0xeca8
+     LDR 	R4, =0x20000104
+     LDR 	R5, =0x10000000
+     
+    ;//cruReg->CRU_MODE_CON = 0x33330000;    //cpu enter slow mode
+    LDR		R8, =0x20000040
+    LDR		R9, =0x33330000
+    #STR	R9, [R8,#0]
+
+     
+     
+     #STR 	R5, [R7,#0]
+     #STR 	R3, [R4,#0]
+
+     bx r6
+ENDPROC(ResetCpu_3026)
 

arch/arm/cpu/armv7/rk32xx/reset.c

@@ -118,7 +118,7 @@ void reset_cpu(ulong ignored)
 #ifndef CONFIG_SYS_ICACHE_OFF
 	icache_disable();
 #endif
-
+	ResetCpu_3026(0x20008140);
 	/* cpu soft reset */
 	rkcru_cpu_soft_reset();
 }

include/power/rk816_pmic.h

@@ -8,6 +8,12 @@
 #include <power/pmic.h>
 #include <fdtdec.h>
 
+#define COMPAT_ROCKCHIP_RK805		"rockchip,rk805"
+#define RK805_NUM_REGULATORS		7
+#define RK805_I2C_ADDR			0x18
+#define RK805_DCDC_EN_REG		0x23
+#define RK805_LDO_EN_REG		0x27
+
 #define COMPAT_ROCKCHIP_RK816		"rockchip,rk816"
 #define RK816_I2C_ADDR			0x1a
 #define RK816_I2C_SPEED			200000
@@ -154,11 +160,12 @@
 #define	RK816_NEW_FCC_REG2		0xE7
 #define	RK816_NEW_FCC_REG1		0xE8
 #define	RK816_NEW_FCC_REG0		0xE9
-#define RK816_NON_ACT_TIMER_CNT_SAVE	0xEA
+#define RK816_NON_ACT_TIMER_CNT_SAVE_REG 0xEA
 #define RK816_OCV_VOL_VALID_REG		0xEB
 #define RK816_REBOOT_CNT_REG		0xEC
-#define RK816_PCB_IOFFSET_REG		0xED
+#define RK816_POFFSET_REG		0xED
 #define RK816_MISC_MARK_REG		0xEE
+#define RK816_HALT_CNT_REG          0xEF
 #define DATA15_REG			0xEF
 #define DATA16_REG			0xF0
 #define DATA17_REG			0xF1
@@ -167,6 +174,20 @@
 struct pmic_rk816 {
 	struct pmic *pmic;
 	int node;	/*device tree node*/
+	char *name;
+	struct fdt_regulator_match *reg_match;
+	struct fdt_regulator_match *reg1_match;
+	int reg_nums;
+	int (*pre_init_regulator)(unsigned char bus, uchar addr);
+	int (*enable_regulator)(int id);
+	int (*disable_regulator)(int id);
+	int (*fg_init)(unsigned char bus, uchar addr);
+};
+
+struct of_device_id {
+	const char name[32];
+	const char compatible[32];
+	const void *data;
 };
 
 #endif

include/power/rk816_pmic_bak.h

+/*
+ * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __RK816_PMIC_H__
+#define __RK816_PMIC_H__
+#include <power/pmic.h>
+#include <fdtdec.h>
+
+#define COMPAT_ROCKCHIP_RK816		"rockchip,rk816"
+#define RK816_I2C_ADDR			0x1a
+#define RK816_I2C_SPEED			200000
+#define RK816_NUM_REGULATORS		10
+
+#define RK816_VOLT_MASK			0x3f
+#define RK816_SECONDS_REG		0x00
+
+/*VERSION REGISTER*/
+#define RK816_CHIP_NAME_REG		0x17
+#define RK816_CHIP_VER_REG		0x18
+#define RK816_OTP_VER_REG		0x19
+
+/*POWER ON/OFF REGISTER*/
+#define RK816_VB_MON_REG		0x21
+#define RK816_THERMAL_REG		0x22
+#define RK816_PWRON_LP_INT_TIME_REG	0x47
+#define RK816_PWRON_DB_REG		0x48
+#define RK816_DEV_CTRL_REG		0x4B
+#define RK816_ON_SOURCE_REG		0xAE
+#define RK816_OFF_SOURCE_REG		0xAF
+
+/*POWER CHANNELS ENABLE REGISTER*/
+#define RK816_DCDC_EN_REG1		0x23
+#define RK816_DCDC_EN_REG2		0x24
+#define RK816_SLP_DCDC_EN_REG		0x25
+#define RK816_SLP_LDO_EN_REG		0x26
+#define RK816_LDO_EN_REG1		0x27
+#define RK816_LDO_EN_REG2		0x28
+
+/*BUCK AND LDO CONFIG REGISTER*/
+#define RK816_SW_BUCK_LDO_CONFIG_REG	0x2A
+#define RK816_SW2_CONFIG_REG		0xA6
+#define RK816_BUCK5_ON_VSEL_REG		0x2B
+#define RK816_BUCK5_SLP_VSEL_REG	0x2C
+#define RK816_BUCK5_CONFIG_REG		0x2D
+#define RK816_BUCK1_CONFIG_REG		0x2E
+#define RK816_BUCK1_ON_VSEL_REG		0x2F
+#define RK816_BUCK1_SLP_VSEL_REG	0x30
+#define RK816_BUCK2_CONFIG_REG		0x32
+#define RK816_BUCK2_ON_VSEL_REG		0x33
+#define RK816_BUCK2_SLP_VSEL_REG	0x34
+#define RK816_BUCK3_CONFIG_REG		0x36
+#define RK816_BUCK4_CONFIG_REG		0x37
+#define RK816_BUCK4_ON_VSEL_REG		0x38
+#define RK816_BUCK4_SLP_VSEL_REG	0x39
+#define RK816_LDO1_ON_VSEL_REG		0x3B
+#define RK816_LDO1_SLP_VSEL_REG		0x3C
+#define RK816_LDO2_ON_VSEL_REG		0x3D
+#define RK816_LDO2_SLP_VSEL_REG		0x3E
+#define RK816_LDO3_ON_VSEL_REG		0x3F
+#define RK816_LDO3_SLP_VSEL_REG		0x40
+#define RK816_LDO4_ON_VSEL_REG		0x41
+#define RK816_LDO4_SLP_VSEL_REG		0x42
+#define RK816_LDO5_ON_VSEL_REG		0x43
+#define RK816_LDO5_SLP_VSEL_REG		0x44
+#define RK816_LDO6_ON_VSEL_REG		0x45
+#define RK816_LDO6_SLP_VSEL_REG		0x46
+
+/*INTERRUPT REGISTER*/
+#define RK816_INT_STS_REG1		0x49
+#define RK816_INT_STS_MSK_REG1		0x4A
+#define RK816_INT_STS_REG2		0x4C
+#define RK816_INT_STS_MSK_REG2		0x4D
+#define RK816_INT_STS_REG3		0x4E
+#define RK816_INT_STS_MSK_REG3		0x4F
+#define RK816_GPIO_IO_POL_REG		0x50
+
+/*CHARGER BOOST AND OTG REGISTER*/
+#define RK816_OTG_BUCK_LDO_CONFIG_REG	0x2A
+#define RK816_CHRG_CONFIG_REG		0x2B
+#define RK816_BOOST_ON_VESL_REG		0x54
+#define RK816_BOOST_SLP_VSEL_REG	0x55
+#define RK816_CHRG_BOOST_CONFIG_REG	0x9A
+#define RK816_SUP_STS_REG		0xA0
+#define RK816_USB_CTRL_REG		0xA1
+#define RK816_CHRG_CTRL_REG1		0xA3
+#define RK816_CHRG_CTRL_REG2		0xA4
+#define RK816_CHRG_CTRL_REG3		0xA5
+#define RK816_BAT_CTRL_REG		0xA6
+#define RK816_BAT_HTS_TS_REG		0xA8
+#define RK816_BAT_LTS_TS_REG		0xA9
+
+/*ADC AND FUEL GAUGE REGISTER*/
+#define RK816_TS_CTRL_REG		0xAC
+#define RK816_ADC_CTRL_REG		0xAD
+#define RK816_GGCON_REG			0xB0
+#define RK816_GGSTS_REG			0xB1
+#define RK816_ZERO_CUR_ADC_REGH		0xB2
+#define RK816_ZERO_CUR_ADC_REGL		0xB3
+#define RK816_GASCNT_CAL_REG3		0xB4
+#define RK816_GASCNT_CAL_REG2		0xB5
+#define RK816_GASCNT_CAL_REG1		0xB6
+#define RK816_GASCNT_CAL_REG0		0xB7
+#define RK816_GASCNT_REG3		0xB8
+#define RK816_GASCNT_REG2		0xB9
+#define RK816_GASCNT_REG1		0xBA
+#define RK816_GASCNT_REG0		0xBB
+#define RK816_BAT_CUR_AVG_REGH		0xBC
+#define RK816_BAT_CUR_AVG_REGL		0xBD
+#define RK816_TS_ADC_REGH		0xBE
+#define RK816_TS_ADC_REGL		0xBF
+#define RK816_USB_ADC_REGH		0xC0
+#define RK816_USB_ADC_REGL		0xC1
+#define RK816_BAT_OCV_REGH		0xC2
+#define RK816_BAT_OCV_REGL		0xC3
+#define RK816_BAT_VOL_REGH		0xC4
+#define RK816_BAT_VOL_REGL		0xC5
+#define RK816_RELAX_ENTRY_THRES_REGH	0xC6
+#define RK816_RELAX_ENTRY_THRES_REGL	0xC7
+#define RK816_RELAX_EXIT_THRES_REGH	0xC8
+#define RK816_RELAX_EXIT_THRES_REGL	0xC9
+#define RK816_RELAX_VOL1_REGH		0xCA
+#define RK816_RELAX_VOL1_REGL		0xCB
+#define RK816_RELAX_VOL2_REGH		0xCC
+#define RK816_RELAX_VOL2_REGL		0xCD
+#define RK816_RELAX_CUR1_REGH		0xCE
+#define RK816_RELAX_CUR1_REGL		0xCF
+#define RK816_RELAX_CUR2_REGH		0xD0
+#define RK816_RELAX_CUR2_REGL		0xD1
+#define RK816_CAL_OFFSET_REGH		0xD2
+#define RK816_CAL_OFFSET_REGL		0xD3
+#define RK816_NON_ACT_TIMER_CNT_REG	0xD4
+#define RK816_VCALIB0_REGH		0xD5
+#define RK816_VCALIB0_REGL		0xD6
+#define RK816_VCALIB1_REGH		0xD7
+#define RK816_VCALIB1_REGL		0xD8
+#define RK816_FCC_GASCNT_REG3		0xD9
+#define RK816_FCC_GASCNT_REG2		0xDA
+#define RK816_FCC_GASCNT_REG1		0xDB
+#define RK816_FCC_GASCNT_REG0		0xDC
+#define RK816_IOFFSET_REGH		0xDD
+#define RK816_IOFFSET_REGL		0xDE
+#define RK816_SLEEP_CON_SAMP_CUR_REG	0xDF
+
+/*DATA REGISTER*/
+#define RK816_SOC_REG			0xE0
+#define	RK816_REMAIN_CAP_REG3		0xE1
+#define	RK816_REMAIN_CAP_REG2		0xE2
+#define	RK816_REMAIN_CAP_REG1		0xE3
+#define	RK816_REMAIN_CAP_REG0		0xE4
+#define	RK816_UPDAT_LEVE_REG		0xE5
+#define	RK816_NEW_FCC_REG3		0xE6
+#define	RK816_NEW_FCC_REG2		0xE7
+#define	RK816_NEW_FCC_REG1		0xE8
+#define	RK816_NEW_FCC_REG0		0xE9
+#define RK816_NON_ACT_TIMER_CNT_SAVE	0xEA
+#define RK816_OCV_VOL_VALID_REG		0xEB
+#define RK816_REBOOT_CNT_REG		0xEC
+#define RK816_PCB_IOFFSET_REG		0xED
+#define RK816_MISC_MARK_REG		0xEE
+#define DATA15_REG			0xEF
+#define DATA16_REG			0xF0
+#define DATA17_REG			0xF1
+#define DATA18_REG			0xF2
+
+struct pmic_rk816 {
+	struct pmic *pmic;
+	int node;	/*device tree node*/
+};
+
+#endif