Cleanup (PPC4xx is AMCC now)

CHANGELOG

@@ -2,6 +2,8 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Cleanup (PPC4xx is AMCC now)
+
 * esd CPCI2DP board added
   Patch by Matthias Fuchs, 22 Sep 2005
 

CREDITS

@@ -340,7 +340,7 @@ W: http://www.windriver.com
 
 N: Stefan Roese
 E: stefan.roese@esd-electronics.com
-D: IBM PPC401/403/405GP Support; Windows environment support
+D: AMCC PPC401/403/405GP Support; Windows environment support
 
 N: Erwin Rol
 E: erwin@muffin.org
@@ -356,7 +356,7 @@ D: Author of LiMon-1.4.2, which contributed some ideas
 
 N: Travis B. Sawyer
 E: travis.sawyer@sandburst.com
-D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.  IBM 440gx Ref Platform (Ocotea)
+D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board.  AMCC 440gx Ref Platform (Ocotea)
 
 N: Paolo Scaffardi
 E: arsenio@tin.it

README

@@ -145,7 +145,7 @@ Directory Hierarchy:
   - mpc85xx	Files specific to Freescale MPC85xx CPUs
   - nios	Files specific to Altera NIOS CPUs
   - nios2	Files specific to Altera Nios-II CPUs
-  - ppc4xx	Files specific to IBM PowerPC 4xx CPUs
+  - ppc4xx	Files specific to AMCC PowerPC 4xx CPUs
   - pxa		Files specific to Intel XScale PXA CPUs
   - s3c44b0	Files specific to Samsung S3C44B0 CPUs
   - sa1100	Files specific to Intel StrongARM SA1100 CPUs
@@ -497,7 +497,7 @@ The following options need to be configured:
 - Console UART Number:
 		CONFIG_UART1_CONSOLE
 
-		IBM PPC4xx only.
+		AMCC PPC4xx only.
 		If defined internal UART1 (and not UART0) is used
 		as default U-Boot console.
 

board/MAI/AmigaOneG3SE/ps2kbd.c

@@ -656,7 +656,7 @@ char * kbd_initialize(void)
 			      | KBD_MODE_DISABLE_MOUSE
 			      | KBD_MODE_KCC);
 
-	/* ibm powerpc portables need this to use scan-code set 1 -- Cort */
+	/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
 	kbd_write_command_w(KBD_CCMD_READ_MODE);
 	if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
 		/*

board/amcc/ocotea/config.mk

@@ -22,7 +22,7 @@
 #
 
 #
-# IBM 440GX Reference Platform (Ocotea) board
+# AMCC 440GX Reference Platform (Ocotea) board
 #
 
 #TEXT_BASE = 0xFFFE0000

board/dave/PPChameleonEVB/PPChameleonEVB.c

@@ -279,10 +279,10 @@ void video_get_info_str (int line_number, char *info)
 	case 1:
 		switch (pvr) {
 		case PVR_405EP_RB:
-			sprintf (info, " IBM PowerPC 405EP Rev. B");
+			sprintf (info, " AMCC PowerPC 405EP Rev. B");
 			break;
 		default:
-			sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
+			sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
 			break;
 		}
 		return;

board/eric/eric.c

@@ -26,10 +26,10 @@
 #include "eric.h"
 #include <asm/processor.h>
 
-#define IBM405GP_GPIO0_OR      0xef600700	/* GPIO Output */
-#define IBM405GP_GPIO0_TCR     0xef600704	/* GPIO Three-State Control */
-#define IBM405GP_GPIO0_ODR     0xef600718	/* GPIO Open Drain */
-#define IBM405GP_GPIO0_IR      0xef60071c	/* GPIO Input */
+#define PPC405GP_GPIO0_OR      0xef600700	/* GPIO Output */
+#define PPC405GP_GPIO0_TCR     0xef600704	/* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR     0xef600718	/* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR      0xef60071c	/* GPIO Input */
 
 int board_early_init_f (void)
 {
@@ -50,7 +50,7 @@ int board_early_init_f (void)
    |       IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
    |       IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
    |        -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
-   |           IBM405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in IBM405GP_GPIO0_OR,
+   |           PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR,
    |           else tristate)
    | Note for ERIC board:
    |       An interrupt taken for the HOST (IRQ 28) indicates that
@@ -70,8 +70,8 @@ int board_early_init_f (void)
 
 	mtdcr (cntrl0, 0x00002000);	/* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
 
-	out32 (IBM405GP_GPIO0_OR, 0x60000000);	/*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
-	out32 (IBM405GP_GPIO0_TCR, 0x7E400000);
+	out32 (PPC405GP_GPIO0_OR, 0x60000000);	/*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
+	out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
 
 	return 0;
 }

board/esd/ocrtc/cmd_ocrtc.c

@@ -29,8 +29,8 @@
 
 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
 
-#define IBM_VENDOR_ID    0x1014
-#define PPC405_DEVICE_ID 0x0156
+#define AMCC_VENDOR_ID		0x1014
+#define PPC405_DEVICE_ID	0x0156
 
 
 /*
@@ -43,7 +43,7 @@ int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	u32 addr;
 
 	while (bdf >= 0) {
-		if ((bdf = pci_find_device(IBM_VENDOR_ID, PPC405_DEVICE_ID, idx++)) < 0) {
+		if ((bdf = pci_find_device(AMCC_VENDOR_ID, PPC405_DEVICE_ID, idx++)) < 0) {
 			break;
 		}
 		printf("Found device nr %d at %x!\n", idx-1, bdf);

board/mpl/common/kbd.c

@@ -613,7 +613,7 @@ char * kbd_initialize(void)
 			      | KBD_MODE_DISABLE_MOUSE
 			      | KBD_MODE_KCC);
 
-	/* ibm powerpc portables need this to use scan-code set 1 -- Cort */
+	/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
 	kbd_write_command_w(KBD_CCMD_READ_MODE);
 	if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
 		/*

board/mpl/common/pci_parts.h

@@ -137,7 +137,7 @@ static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
 	{ }					    /* end of device table 	*/
 };
 /* PPC405 Dummy only used to prevent autosetup on this host bridge */
-static struct pci_pip405_config_entry ibm405_dummy[] = {
+static struct pci_pip405_config_entry ppc405_dummy[] = {
 	{ }				    	    /* end of device table 	*/
 };
 
@@ -150,7 +150,7 @@ static struct pci_config_table pci_pip405_config_table[]={
 	 PCI_DEVICE_ID_IBM_405GP,
 	 PCI_ANY_ID,
 	 PCI_ANY_ID, PCI_ANY_ID, 0,
-	 pci_pip405_write_regs, {(unsigned long) ibm405_dummy}},
+	 pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
 
 	{PCI_VENDOR_ID_INTEL, 			/* PIIX4 ISA Bridge Function 0 */
 	 PCI_DEVICE_ID_INTEL_82371AB_0,

board/w7o/fpga.c

@@ -77,17 +77,17 @@ fpgaDownload(unsigned char *saddr,
     dest = (unsigned short *)daddr;
 
     /* Get DCR output register */
-    grego = in32(IBM405GP_GPIO0_OR);
+    grego = in32(PPC405GP_GPIO0_OR);
 
     /* Reset FPGA */
     grego &= ~GPIO_XCV_PROG;			/* PROG line low */
-    out32(IBM405GP_GPIO0_OR, grego);
+    out32(PPC405GP_GPIO0_OR, grego);
 
     /* Setup timeout timer */
     start = get_timer(0);
 
     /* Wait for FPGA init line */
-    while(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
+    while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
 	/* Check for timeout - 100us max, so use 3ms */
 	if (get_timer(start) > 3) {
 	    printf("     failed to start init.\n");
@@ -100,10 +100,10 @@ fpgaDownload(unsigned char *saddr,
 
     /* Unreset FPGA */
     grego |= GPIO_XCV_PROG;			/* PROG line high */
-    out32(IBM405GP_GPIO0_OR, grego);
+    out32(PPC405GP_GPIO0_OR, grego);
 
     /* Wait for FPGA end of init period .  */
-    while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
+    while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
 
 	/* Check for timeout */
 	if (get_timer(start) > 3) {
@@ -112,7 +112,7 @@ fpgaDownload(unsigned char *saddr,
 
 	    /* Reset FPGA */
 	    grego &= ~GPIO_XCV_PROG;		/* PROG line low */
-	    out32(IBM405GP_GPIO0_OR, grego);
+	    out32(PPC405GP_GPIO0_OR, grego);
 
 	    goto done;
 	}
@@ -127,18 +127,18 @@ fpgaDownload(unsigned char *saddr,
 	mtdcr(CPC0_CR0, greg);			/*  ... just do it */
 
 	/* turn on open drain for CNFG */
-	greg = in32(IBM405GP_GPIO0_ODR);	/* get open drain register */
+	greg = in32(PPC405GP_GPIO0_ODR);	/* get open drain register */
 	greg |= cnfg;				/* CNFG open drain */
-	out32(IBM405GP_GPIO0_ODR, greg);	/*  .. just do it */
+	out32(PPC405GP_GPIO0_ODR, greg);	/*  .. just do it */
 
 	/* Turn output enable on for CNFG */
-	greg = in32(IBM405GP_GPIO0_TCR);	/* get tristate register */
+	greg = in32(PPC405GP_GPIO0_TCR);	/* get tristate register */
 	greg |= cnfg;				/* CNFG tristate inactive */
-	out32(IBM405GP_GPIO0_TCR, greg);	/*  ... just do it */
+	out32(PPC405GP_GPIO0_TCR, greg);	/*  ... just do it */
 
 	/* Setup FPGA for programming */
 	grego &= ~cnfg;				/* CONFIG line low */
-	out32(IBM405GP_GPIO0_OR, grego);
+	out32(PPC405GP_GPIO0_OR, grego);
 
 	/*
 	 * Program the FPGA
@@ -149,12 +149,12 @@ fpgaDownload(unsigned char *saddr,
 
 	/* Done programming */
 	grego |= cnfg;				/* CONFIG line high */
-	out32(IBM405GP_GPIO0_OR, grego);
+	out32(PPC405GP_GPIO0_OR, grego);
 
 	/* Turn output enable OFF for CNFG */
-	greg = in32(IBM405GP_GPIO0_TCR);	/* get tristate register */
+	greg = in32(PPC405GP_GPIO0_TCR);	/* get tristate register */
 	greg &= ~cnfg;				/* CNFG tristate inactive */
-	out32(IBM405GP_GPIO0_TCR, greg);	/*  ... just do it */
+	out32(PPC405GP_GPIO0_TCR, greg);	/*  ... just do it */
 
 	/* Toggle IRQ/GPIO */
 	greg = mfdcr(CPC0_CR0);			/* get chip ctrl register */
@@ -180,7 +180,7 @@ fpgaDownload(unsigned char *saddr,
     start = get_timer(0);
 
     /* Wait for FPGA end of programming period .  */
-    while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
+    while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
 
 	/* Check for timeout */
 	if (get_timer(start) > 3) {
@@ -189,7 +189,7 @@ fpgaDownload(unsigned char *saddr,
 
 	    /* Reset FPGA */
 	    grego &= ~GPIO_XCV_PROG;		/* PROG line low */
-	    out32(IBM405GP_GPIO0_OR, grego);
+	    out32(PPC405GP_GPIO0_OR, grego);
 
 	    goto done;
 	}

board/w7o/w7o.c

@@ -47,9 +47,9 @@ int board_early_init_f (void)
 	/*
 	 * Setup GPIO pins - reset devices.
 	 */
-	out32 (IBM405GP_GPIO0_ODR, 0x10000000);	/* one open drain pin */
-	out32 (IBM405GP_GPIO0_OR, 0x3E000000);	/* set output pins to default */
-	out32 (IBM405GP_GPIO0_TCR, 0x7f800000);	/* setup for output */
+	out32 (PPC405GP_GPIO0_ODR, 0x10000000);	/* one open drain pin */
+	out32 (PPC405GP_GPIO0_OR, 0x3E000000);	/* set output pins to default */
+	out32 (PPC405GP_GPIO0_TCR, 0x7f800000);	/* setup for output */
 
 	/*
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -78,9 +78,9 @@ int board_early_init_f (void)
 	/*
 	 * Setup GPIO pins
 	 */
-	out32 (IBM405GP_GPIO0_ODR, 0x01800000);	/* XCV Done Open Drain */
-	out32 (IBM405GP_GPIO0_OR, 0x03800000);	/* set out pins to default */
-	out32 (IBM405GP_GPIO0_TCR, 0x66C00000);	/* setup for output */
+	out32 (PPC405GP_GPIO0_ODR, 0x01800000);	/* XCV Done Open Drain */
+	out32 (PPC405GP_GPIO0_OR, 0x03800000);	/* set out pins to default */
+	out32 (PPC405GP_GPIO0_TCR, 0x66C00000);	/* setup for output */
 
 	/*
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -238,14 +238,14 @@ int misc_init_r (void)
 #if defined(CONFIG_W7OLMG)
 	unsigned long greg;	/* GPIO Register */
 
-	greg = in32 (IBM405GP_GPIO0_OR);
+	greg = in32 (PPC405GP_GPIO0_OR);
 
 	/*
 	 * XXX - Unreset devices - this should be moved into VxWorks driver code
 	 */
 	greg |= 0x41800000L;	/* SAM, PHY, Galileo */
 
-	out32 (IBM405GP_GPIO0_OR, greg);	/* set output pins to default */
+	out32 (PPC405GP_GPIO0_OR, greg);	/* set output pins to default */
 #endif /* CONFIG_W7OLMG */
 
 	/*

board/w7o/w7o.h

@@ -25,13 +25,13 @@
 #define _W7O_H_
 #include <config.h>
 
-/* IBM 405GP PowerPC GPIO registers */
-#define IBM405GP_GPIO0_OR	0xef600700L	/* GPIO Output */
-#define IBM405GP_GPIO0_TCR	0xef600704L	/* GPIO Three-State Control */
-#define IBM405GP_GPIO0_ODR	0xef600718L	/* GPIO Open Drain */
-#define IBM405GP_GPIO0_IR	0xef60071cL	/* GPIO Input */
+/* AMCC 405GP PowerPC GPIO registers */
+#define PPC405GP_GPIO0_OR	0xef600700L	/* GPIO Output */
+#define PPC405GP_GPIO0_TCR	0xef600704L	/* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR	0xef600718L	/* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR	0xef60071cL	/* GPIO Input */
 
-/* IBM 405GP DCRs */
+/* AMCC 405GP DCRs */
 #define CPC0_CR0		0xb1		/* Chip control register 0 */
 
 /* LMG FPGA <=> CPU GPIO signals */

common/cmd_dcr.c

@@ -22,7 +22,7 @@
  */
 
 /*
- * IBM 4XX DCR Functions
+ * AMCC 4XX DCR Functions
  */
 
 #include <common.h>
@@ -31,89 +31,91 @@
 
 #if defined(CONFIG_4xx) && (CONFIG_COMMANDS & CFG_CMD_SETGETDCR)
 
-/* ======================================================================
- * Interpreter command to retrieve an IBM PPC 4xx Device Control Register
- * ======================================================================
+/* =======================================================================
+ * Interpreter command to retrieve an AMCC PPC 4xx Device Control Register
+ * =======================================================================
  */
 int do_getdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 {
-    unsigned short dcrn;                     /* Device Control Register Num */
-    unsigned long value;                     /* DCR's value */
+	unsigned short dcrn;	/* Device Control Register Num */
+	unsigned long value;	/* DCR's value */
 
-    unsigned long get_dcr(unsigned short);
+	unsigned long get_dcr (unsigned short);
 
-    /* Validate arguments */
-    if (argc < 2) {
-	printf("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    }
+	/* Validate arguments */
+	if (argc < 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
 
-    /* Get a DCR */
-    dcrn = (unsigned short)simple_strtoul(argv[ 1 ], NULL, 16);
-    value = get_dcr(dcrn);
+	/* Get a DCR */
+	dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
+	value = get_dcr (dcrn);
 
-    printf("%04x: %08lx\n", dcrn, value);
+	printf ("%04x: %08lx\n", dcrn, value);
 
-    return 0;
-} /* do_getdcr */
+	return 0;
+}
 
 
 /* ======================================================================
- * Interpreter command to set an IBM PPC 4xx Device Control Register
+ * Interpreter command to set an AMCC PPC 4xx Device Control Register
  * ======================================================================
 */
-int do_setdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-   unsigned long get_dcr(unsigned short );
-   unsigned long set_dcr(unsigned short , unsigned long );
-    unsigned short dcrn;                     /* Device Control Register Num */
-   unsigned long value;
-		    /* DCR's value */
-    int nbytes;
-    extern char console_buffer[];
-
-    /* Validate arguments */
-    if (argc < 2) {
-	printf("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    }
-
-    /* Set a DCR */
-    dcrn = (unsigned short)simple_strtoul(argv[1], NULL, 16);
-    do {
-	value = get_dcr(dcrn);
-	printf("%04x: %08lx", dcrn, value);
-	nbytes = readline(" ? ");
-	if (nbytes == 0) {
-	    /*
-	     * <CR> pressed as only input, don't modify current
-	     * location and exit command.
-	     */
-	    nbytes = 1;
-	    return 0;
-	} else {
-	    unsigned long i;
-	    char *endp;
-	    i = simple_strtoul(console_buffer, &endp, 16);
-	    nbytes = endp - console_buffer;
-	    if (nbytes)
-		set_dcr(dcrn, i);
+	unsigned long get_dcr (unsigned short);
+	unsigned long set_dcr (unsigned short, unsigned long);
+	unsigned short dcrn;	/* Device Control Register Num */
+	unsigned long value;
+
+	/* DCR's value */
+	int nbytes;
+	extern char console_buffer[];
+
+	/* Validate arguments */
+	if (argc < 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
 	}
-    } while (nbytes);
 
-    return 0;
-} /* do_setdcr */
+	/* Set a DCR */
+	dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
+	do {
+		value = get_dcr (dcrn);
+		printf ("%04x: %08lx", dcrn, value);
+		nbytes = readline (" ? ");
+		if (nbytes == 0) {
+			/*
+			 * <CR> pressed as only input, don't modify current
+			 * location and exit command.
+			 */
+			nbytes = 1;
+			return 0;
+		} else {
+			unsigned long i;
+			char *endp;
+
+			i = simple_strtoul (console_buffer, &endp, 16);
+			nbytes = endp - console_buffer;
+			if (nbytes)
+				set_dcr (dcrn, i);
+		}
+	} while (nbytes);
+
+	return 0;
+}
 
 /***************************************************/
 
 U_BOOT_CMD(
 	getdcr,	2,	1,	do_getdcr,
-	"getdcr  - Get an IBM PPC 4xx DCR's value\n",
+	"getdcr  - Get an AMCC PPC 4xx DCR's value\n",
 	"dcrn - return a DCR's value.\n"
 );
 U_BOOT_CMD(
 	setdcr,	2,	1,	do_setdcr,
-	"setdcr  - Set an IBM PPC 4xx DCR's value\n",
+	"setdcr  - Set an AMCC PPC 4xx DCR's value\n",
 	"dcrn - set a DCR's value.\n"
 );
 

cpu/ppc4xx/4xx_enet.c

@@ -90,7 +90,7 @@
 #include "vecnum.h"
 
 /*
- * Only compile for platform with IBM/AMCC EMAC ethernet controller and
+ * Only compile for platform with AMCC EMAC ethernet controller and
  * network support enabled.
  * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
  */

cpu/ppc4xx/bedbug_405.c

@@ -25,7 +25,7 @@ int bedbug405_clear __P ((int));
 
 
 /* ======================================================================
- * Initialize the global bug_ctx structure for the IBM PPC405.	Clear all
+ * Initialize the global bug_ctx structure for the AMCC PPC405.	Clear all
  * of the breakpoints.
  * ====================================================================== */
 

cpu/ppc4xx/serial.c

@@ -320,7 +320,7 @@ int serial_tstc ()
 #endif
 
 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
-#error "External serial clock not supported on IBM PPC405EP!"
+#error "External serial clock not supported on AMCC PPC405EP!"
 #endif
 
 #define UART_RBR    0x00

cpu/ppc4xx/spd_sdram.c

@@ -14,7 +14,7 @@
  *
  * (C) Copyright 2002
  * Jun Gu, Artesyn Technology, jung@artesyncp.com
- * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
+ * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  *
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -108,7 +108,7 @@ int spd_read(uint addr);
  * This function is reading data from the DIMM module EEPROM over the SPD bus
  * and uses that to program the sdram controller.
  *
- * This works on boards that has the same schematics that the IBM walnut has.
+ * This works on boards that has the same schematics that the AMCC walnut has.
  *
  * Input: null for default I2C spd functions or a pointer to a custom function
  * returning spd_data.
@@ -696,7 +696,7 @@ long  program_bxcr(unsigned long* dimm_populated,
  * This function is reading data from the DIMM module EEPROM over the SPD bus
  * and uses that to program the sdram controller.
  *
- * This works on boards that has the same schematics that the IBM walnut has.
+ * This works on boards that has the same schematics that the AMCC walnut has.
  *
  * BUG: Don't handle ECC memory
  * BUG: A few values in the TR register is currently hardcoded

cpu/ppc4xx/start.S

@@ -42,7 +42,7 @@
 /*	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
 /*------------------------------------------------------------------------------- */
 
-/*  U-Boot - Startup Code for IBM 4xx PowerPC based Embedded Boards
+/*  U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
  *
  *
  *  The processor starts at 0xfffffffc and the code is executed

doc/I2C_Edge_Conditions

@@ -28,7 +28,7 @@ I2C Edge Conditions:
 
 Notes
 -----
-!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!!
+!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!!
 
 This reset edge condition could possibly be present in every I2C
 controller and device available. For boards where a I2C bus reset