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Commit d1bdfe37 authored by Mark Stevens's avatar Mark Stevens
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update from duco/rk312x_20160510 on rockchip-5.1.0_r5 branches

parent 23e1ad66
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arch/arm/dts/include/dt-bindings 0 → 120000
View file @ d1bdfe37
../../../../include/dt-bindings
\ No newline at end of file
arch/arm/dts/include/dt-bindings/clock/tegra114-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra114-car.
*
* The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 160 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
/* 0 */
/* 1 */
/* 2 */
/* 3 */
#define TEGRA114_CLK_RTC 4
#define TEGRA114_CLK_TIMER 5
#define TEGRA114_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA114_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA114_CLK_I2S1 11
#define TEGRA114_CLK_I2C1 12
#define TEGRA114_CLK_NDFLASH 13
#define TEGRA114_CLK_SDMMC1 14
#define TEGRA114_CLK_SDMMC4 15
/* 16 */
#define TEGRA114_CLK_PWM 17
#define TEGRA114_CLK_I2S2 18
#define TEGRA114_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA114_CLK_GR2D 21
#define TEGRA114_CLK_USBD 22
#define TEGRA114_CLK_ISP 23
#define TEGRA114_CLK_GR3D 24
/* 25 */
#define TEGRA114_CLK_DISP2 26
#define TEGRA114_CLK_DISP1 27
#define TEGRA114_CLK_HOST1X 28
#define TEGRA114_CLK_VCP 29
#define TEGRA114_CLK_I2S0 30
/* 31 */
/* 32 */
/* 33 */
#define TEGRA114_CLK_APBDMA 34
/* 35 */
#define TEGRA114_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA114_CLK_KFUSE 40
#define TEGRA114_CLK_SBC1 41
#define TEGRA114_CLK_NOR 42
/* 43 */
#define TEGRA114_CLK_SBC2 44
/* 45 */
#define TEGRA114_CLK_SBC3 46
#define TEGRA114_CLK_I2C5 47
#define TEGRA114_CLK_DSIA 48
/* 49 */
#define TEGRA114_CLK_MIPI 50
#define TEGRA114_CLK_HDMI 51
#define TEGRA114_CLK_CSI 52
/* 53 */
#define TEGRA114_CLK_I2C2 54
#define TEGRA114_CLK_UARTC 55
#define TEGRA114_CLK_MIPI_CAL 56
#define TEGRA114_CLK_EMC 57
#define TEGRA114_CLK_USB2 58
#define TEGRA114_CLK_USB3 59
/* 60 */
#define TEGRA114_CLK_VDE 61
#define TEGRA114_CLK_BSEA 62
#define TEGRA114_CLK_BSEV 63
/* 64 */
#define TEGRA114_CLK_UARTD 65
/* 66 */
#define TEGRA114_CLK_I2C3 67
#define TEGRA114_CLK_SBC4 68
#define TEGRA114_CLK_SDMMC3 69
/* 70 */
#define TEGRA114_CLK_OWR 71
/* 72 */
#define TEGRA114_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA114_CLK_LA 76
#define TEGRA114_CLK_TRACE 77
#define TEGRA114_CLK_SOC_THERM 78
#define TEGRA114_CLK_DTV 79
#define TEGRA114_CLK_NDSPEED 80
#define TEGRA114_CLK_I2CSLOW 81
#define TEGRA114_CLK_DSIB 82
#define TEGRA114_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA114_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA114_CLK_MSENC 91
#define TEGRA114_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA114_CLK_MSELECT 99
#define TEGRA114_CLK_TSENSOR 100
#define TEGRA114_CLK_I2S3 101
#define TEGRA114_CLK_I2S4 102
#define TEGRA114_CLK_I2C4 103
#define TEGRA114_CLK_SBC5 104
#define TEGRA114_CLK_SBC6 105
#define TEGRA114_CLK_D_AUDIO 106
#define TEGRA114_CLK_APBIF 107
#define TEGRA114_CLK_DAM0 108
#define TEGRA114_CLK_DAM1 109
#define TEGRA114_CLK_DAM2 110
#define TEGRA114_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA114_CLK_AUDIO0_2X 113
#define TEGRA114_CLK_AUDIO1_2X 114
#define TEGRA114_CLK_AUDIO2_2X 115
#define TEGRA114_CLK_AUDIO3_2X 116
#define TEGRA114_CLK_AUDIO4_2X 117
#define TEGRA114_CLK_SPDIF_2X 118
#define TEGRA114_CLK_ACTMON 119
#define TEGRA114_CLK_EXTERN1 120
#define TEGRA114_CLK_EXTERN2 121
#define TEGRA114_CLK_EXTERN3 122
/* 123 */
/* 124 */
#define TEGRA114_CLK_HDA 125
/* 126 */
#define TEGRA114_CLK_SE 127
#define TEGRA114_CLK_HDA2HDMI 128
/* 129 */
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA114_CLK_CILAB 144
#define TEGRA114_CLK_CILCD 145
#define TEGRA114_CLK_CILE 146
#define TEGRA114_CLK_DSIALP 147
#define TEGRA114_CLK_DSIBLP 148
/* 149 */
#define TEGRA114_CLK_DDS 150
/* 151 */
#define TEGRA114_CLK_DP2 152
#define TEGRA114_CLK_AMX 153
#define TEGRA114_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA114_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
/* 166 */
/* 167 */
/* 168 */
/* 169 */
/* 170 */
/* 171 */
/* 172 */
/* 173 */
/* 174 */
/* 175 */
/* 176 */
/* 177 */
/* 178 */
/* 179 */
/* 180 */
/* 181 */
/* 182 */
/* 183 */
/* 184 */
/* 185 */
/* 186 */
/* 187 */
/* 188 */
/* 189 */
/* 190 */
/* 191 */
#define TEGRA114_CLK_UARTB 192
#define TEGRA114_CLK_VFIR 193
#define TEGRA114_CLK_SPDIF_IN 194
#define TEGRA114_CLK_SPDIF_OUT 195
#define TEGRA114_CLK_VI 196
#define TEGRA114_CLK_VI_SENSOR 197
#define TEGRA114_CLK_FUSE 198
#define TEGRA114_CLK_FUSE_BURN 199
#define TEGRA114_CLK_CLK_32K 200
#define TEGRA114_CLK_CLK_M 201
#define TEGRA114_CLK_CLK_M_DIV2 202
#define TEGRA114_CLK_CLK_M_DIV4 203
#define TEGRA114_CLK_PLL_REF 204
#define TEGRA114_CLK_PLL_C 205
#define TEGRA114_CLK_PLL_C_OUT1 206
#define TEGRA114_CLK_PLL_C2 207
#define TEGRA114_CLK_PLL_C3 208
#define TEGRA114_CLK_PLL_M 209
#define TEGRA114_CLK_PLL_M_OUT1 210
#define TEGRA114_CLK_PLL_P 211
#define TEGRA114_CLK_PLL_P_OUT1 212
#define TEGRA114_CLK_PLL_P_OUT2 213
#define TEGRA114_CLK_PLL_P_OUT3 214
#define TEGRA114_CLK_PLL_P_OUT4 215
#define TEGRA114_CLK_PLL_A 216
#define TEGRA114_CLK_PLL_A_OUT0 217
#define TEGRA114_CLK_PLL_D 218
#define TEGRA114_CLK_PLL_D_OUT0 219
#define TEGRA114_CLK_PLL_D2 220
#define TEGRA114_CLK_PLL_D2_OUT0 221
#define TEGRA114_CLK_PLL_U 222
#define TEGRA114_CLK_PLL_U_480M 223
#define TEGRA114_CLK_PLL_U_60M 224
#define TEGRA114_CLK_PLL_U_48M 225
#define TEGRA114_CLK_PLL_U_12M 226
#define TEGRA114_CLK_PLL_X 227
#define TEGRA114_CLK_PLL_X_OUT0 228
#define TEGRA114_CLK_PLL_RE_VCO 229
#define TEGRA114_CLK_PLL_RE_OUT 230
#define TEGRA114_CLK_PLL_E_OUT0 231
#define TEGRA114_CLK_SPDIF_IN_SYNC 232
#define TEGRA114_CLK_I2S0_SYNC 233
#define TEGRA114_CLK_I2S1_SYNC 234
#define TEGRA114_CLK_I2S2_SYNC 235
#define TEGRA114_CLK_I2S3_SYNC 236
#define TEGRA114_CLK_I2S4_SYNC 237
#define TEGRA114_CLK_VIMCLK_SYNC 238
#define TEGRA114_CLK_AUDIO0 239
#define TEGRA114_CLK_AUDIO1 240
#define TEGRA114_CLK_AUDIO2 241
#define TEGRA114_CLK_AUDIO3 242
#define TEGRA114_CLK_AUDIO4 243
#define TEGRA114_CLK_SPDIF 244
#define TEGRA114_CLK_CLK_OUT_1 245
#define TEGRA114_CLK_CLK_OUT_2 246
#define TEGRA114_CLK_CLK_OUT_3 247
#define TEGRA114_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA114_CLK_XUSB_HOST_SRC 252
#define TEGRA114_CLK_XUSB_FALCON_SRC 253
#define TEGRA114_CLK_XUSB_FS_SRC 254
#define TEGRA114_CLK_XUSB_SS_SRC 255
#define TEGRA114_CLK_XUSB_DEV_SRC 256
#define TEGRA114_CLK_XUSB_DEV 257
#define TEGRA114_CLK_XUSB_HS_SRC 258
#define TEGRA114_CLK_SCLK 259
#define TEGRA114_CLK_HCLK 260
#define TEGRA114_CLK_PCLK 261
#define TEGRA114_CLK_CCLK_G 262
#define TEGRA114_CLK_CCLK_LP 263
#define TEGRA114_CLK_DFLL_REF 264
#define TEGRA114_CLK_DFLL_SOC 265
/* 266 */
/* 267 */
/* 268 */
/* 269 */
/* 270 */
/* 271 */
/* 272 */
/* 273 */
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA114_CLK_AUDIO0_MUX 300
#define TEGRA114_CLK_AUDIO1_MUX 301
#define TEGRA114_CLK_AUDIO2_MUX 302
#define TEGRA114_CLK_AUDIO3_MUX 303
#define TEGRA114_CLK_AUDIO4_MUX 304
#define TEGRA114_CLK_SPDIF_MUX 305
#define TEGRA114_CLK_CLK_OUT_1_MUX 306
#define TEGRA114_CLK_CLK_OUT_2_MUX 307
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_CLK_MAX 311
#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
arch/arm/dts/include/dt-bindings/clock/tegra124-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra124-car.
*
* The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 185 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 185 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
/* 0 */
/* 1 */
/* 2 */
#define TEGRA124_CLK_ISPB 3
#define TEGRA124_CLK_RTC 4
#define TEGRA124_CLK_TIMER 5
#define TEGRA124_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA124_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA124_CLK_I2S1 11
#define TEGRA124_CLK_I2C1 12
#define TEGRA124_CLK_NDFLASH 13
#define TEGRA124_CLK_SDMMC1 14
#define TEGRA124_CLK_SDMMC4 15
/* 16 */
#define TEGRA124_CLK_PWM 17
#define TEGRA124_CLK_I2S2 18
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA124_CLK_USBD 22
#define TEGRA124_CLK_ISP 23
/* 26 */
/* 25 */
#define TEGRA124_CLK_DISP2 26
#define TEGRA124_CLK_DISP1 27
#define TEGRA124_CLK_HOST1X 28
#define TEGRA124_CLK_VCP 29
#define TEGRA124_CLK_I2S0 30
/* 31 */
/* 32 */
/* 33 */
#define TEGRA124_CLK_APBDMA 34
/* 35 */
#define TEGRA124_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA124_CLK_KFUSE 40
#define TEGRA124_CLK_SBC1 41
#define TEGRA124_CLK_NOR 42
/* 43 */
#define TEGRA124_CLK_SBC2 44
/* 45 */
#define TEGRA124_CLK_SBC3 46
#define TEGRA124_CLK_I2C5 47
#define TEGRA124_CLK_DSIA 48
/* 49 */
#define TEGRA124_CLK_MIPI 50
#define TEGRA124_CLK_HDMI 51
#define TEGRA124_CLK_CSI 52
/* 53 */
#define TEGRA124_CLK_I2C2 54
#define TEGRA124_CLK_UARTC 55
#define TEGRA124_CLK_MIPI_CAL 56
#define TEGRA124_CLK_EMC 57
#define TEGRA124_CLK_USB2 58
#define TEGRA124_CLK_USB3 59
/* 60 */
#define TEGRA124_CLK_VDE 61
#define TEGRA124_CLK_BSEA 62
#define TEGRA124_CLK_BSEV 63
/* 64 */
#define TEGRA124_CLK_UARTD 65
#define TEGRA124_CLK_UARTE 66
#define TEGRA124_CLK_I2C3 67
#define TEGRA124_CLK_SBC4 68
#define TEGRA124_CLK_SDMMC3 69
#define TEGRA124_CLK_PCIE 70
#define TEGRA124_CLK_OWR 71
#define TEGRA124_CLK_AFI 72
#define TEGRA124_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA124_CLK_LA 76
#define TEGRA124_CLK_TRACE 77
#define TEGRA124_CLK_SOC_THERM 78
#define TEGRA124_CLK_DTV 79
#define TEGRA124_CLK_NDSPEED 80
#define TEGRA124_CLK_I2CSLOW 81
#define TEGRA124_CLK_DSIB 82
#define TEGRA124_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA124_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA124_CLK_MSENC 91
#define TEGRA124_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA124_CLK_MSELECT 99
#define TEGRA124_CLK_TSENSOR 100
#define TEGRA124_CLK_I2S3 101
#define TEGRA124_CLK_I2S4 102
#define TEGRA124_CLK_I2C4 103
#define TEGRA124_CLK_SBC5 104
#define TEGRA124_CLK_SBC6 105
#define TEGRA124_CLK_D_AUDIO 106
#define TEGRA124_CLK_APBIF 107
#define TEGRA124_CLK_DAM0 108
#define TEGRA124_CLK_DAM1 109
#define TEGRA124_CLK_DAM2 110
#define TEGRA124_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA124_CLK_AUDIO0_2X 113
#define TEGRA124_CLK_AUDIO1_2X 114
#define TEGRA124_CLK_AUDIO2_2X 115
#define TEGRA124_CLK_AUDIO3_2X 116
#define TEGRA124_CLK_AUDIO4_2X 117
#define TEGRA124_CLK_SPDIF_2X 118
#define TEGRA124_CLK_ACTMON 119
#define TEGRA124_CLK_EXTERN1 120
#define TEGRA124_CLK_EXTERN2 121
#define TEGRA124_CLK_EXTERN3 122
#define TEGRA124_CLK_SATA_OOB 123
#define TEGRA124_CLK_SATA 124
#define TEGRA124_CLK_HDA 125
/* 126 */
#define TEGRA124_CLK_SE 127
#define TEGRA124_CLK_HDA2HDMI 128
#define TEGRA124_CLK_SATA_COLD 129
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA124_CLK_CILAB 144
#define TEGRA124_CLK_CILCD 145
#define TEGRA124_CLK_CILE 146
#define TEGRA124_CLK_DSIALP 147
#define TEGRA124_CLK_DSIBLP 148
#define TEGRA124_CLK_ENTROPY 149
#define TEGRA124_CLK_DDS 150
/* 151 */
#define TEGRA124_CLK_DP2 152
#define TEGRA124_CLK_AMX 153
#define TEGRA124_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA124_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
#define TEGRA124_CLK_I2C6 166
/* 167 */
/* 168 */
/* 169 */
/* 170 */
#define TEGRA124_CLK_VIM2_CLK 171
/* 172 */
/* 173 */
/* 174 */
/* 175 */
#define TEGRA124_CLK_HDMI_AUDIO 176
#define TEGRA124_CLK_CLK72MHZ 177
#define TEGRA124_CLK_VIC03 178
/* 179 */
#define TEGRA124_CLK_ADX1 180
#define TEGRA124_CLK_DPAUX 181
#define TEGRA124_CLK_SOR0 182
/* 183 */
#define TEGRA124_CLK_GPU 184
#define TEGRA124_CLK_AMX1 185
#define TEGRA124_CLK_AFC0 186
#define TEGRA124_CLK_AFC1 187
#define TEGRA124_CLK_AFC2 188
#define TEGRA124_CLK_AFC3 189
#define TEGRA124_CLK_AFC4 190
#define TEGRA124_CLK_AFC5 191
#define TEGRA124_CLK_UARTB 192
#define TEGRA124_CLK_VFIR 193
#define TEGRA124_CLK_SPDIF_IN 194
#define TEGRA124_CLK_SPDIF_OUT 195
#define TEGRA124_CLK_VI 196
#define TEGRA124_CLK_VI_SENSOR 197
#define TEGRA124_CLK_FUSE 198
#define TEGRA124_CLK_FUSE_BURN 199
#define TEGRA124_CLK_CLK_32K 200
#define TEGRA124_CLK_CLK_M 201
#define TEGRA124_CLK_CLK_M_DIV2 202
#define TEGRA124_CLK_CLK_M_DIV4 203
#define TEGRA124_CLK_PLL_REF 204
#define TEGRA124_CLK_PLL_C 205
#define TEGRA124_CLK_PLL_C_OUT1 206
#define TEGRA124_CLK_PLL_C2 207
#define TEGRA124_CLK_PLL_C3 208
#define TEGRA124_CLK_PLL_M 209
#define TEGRA124_CLK_PLL_M_OUT1 210
#define TEGRA124_CLK_PLL_P 211
#define TEGRA124_CLK_PLL_P_OUT1 212
#define TEGRA124_CLK_PLL_P_OUT2 213
#define TEGRA124_CLK_PLL_P_OUT3 214
#define TEGRA124_CLK_PLL_P_OUT4 215
#define TEGRA124_CLK_PLL_A 216
#define TEGRA124_CLK_PLL_A_OUT0 217
#define TEGRA124_CLK_PLL_D 218
#define TEGRA124_CLK_PLL_D_OUT0 219
#define TEGRA124_CLK_PLL_D2 220
#define TEGRA124_CLK_PLL_D2_OUT0 221
#define TEGRA124_CLK_PLL_U 222
#define TEGRA124_CLK_PLL_U_480M 223
#define TEGRA124_CLK_PLL_U_60M 224
#define TEGRA124_CLK_PLL_U_48M 225
#define TEGRA124_CLK_PLL_U_12M 226
#define TEGRA124_CLK_PLL_X 227
#define TEGRA124_CLK_PLL_X_OUT0 228
#define TEGRA124_CLK_PLL_RE_VCO 229
#define TEGRA124_CLK_PLL_RE_OUT 230
#define TEGRA124_CLK_PLL_E 231
#define TEGRA124_CLK_SPDIF_IN_SYNC 232
#define TEGRA124_CLK_I2S0_SYNC 233
#define TEGRA124_CLK_I2S1_SYNC 234
#define TEGRA124_CLK_I2S2_SYNC 235
#define TEGRA124_CLK_I2S3_SYNC 236
#define TEGRA124_CLK_I2S4_SYNC 237
#define TEGRA124_CLK_VIMCLK_SYNC 238
#define TEGRA124_CLK_AUDIO0 239
#define TEGRA124_CLK_AUDIO1 240
#define TEGRA124_CLK_AUDIO2 241
#define TEGRA124_CLK_AUDIO3 242
#define TEGRA124_CLK_AUDIO4 243
#define TEGRA124_CLK_SPDIF 244
#define TEGRA124_CLK_CLK_OUT_1 245
#define TEGRA124_CLK_CLK_OUT_2 246
#define TEGRA124_CLK_CLK_OUT_3 247
#define TEGRA124_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA124_CLK_XUSB_HOST_SRC 252
#define TEGRA124_CLK_XUSB_FALCON_SRC 253
#define TEGRA124_CLK_XUSB_FS_SRC 254
#define TEGRA124_CLK_XUSB_SS_SRC 255
#define TEGRA124_CLK_XUSB_DEV_SRC 256
#define TEGRA124_CLK_XUSB_DEV 257
#define TEGRA124_CLK_XUSB_HS_SRC 258
#define TEGRA124_CLK_SCLK 259
#define TEGRA124_CLK_HCLK 260
#define TEGRA124_CLK_PCLK 261
#define TEGRA124_CLK_CCLK_G 262
#define TEGRA124_CLK_CCLK_LP 263
#define TEGRA124_CLK_DFLL_REF 264
#define TEGRA124_CLK_DFLL_SOC 265
#define TEGRA124_CLK_VI_SENSOR2 266
#define TEGRA124_CLK_PLL_P_OUT5 267
#define TEGRA124_CLK_CML0 268
#define TEGRA124_CLK_CML1 269
#define TEGRA124_CLK_PLL_C4 270
#define TEGRA124_CLK_PLL_DP 271
#define TEGRA124_CLK_PLL_E_MUX 272
/* 273 */
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA124_CLK_AUDIO0_MUX 300
#define TEGRA124_CLK_AUDIO1_MUX 301
#define TEGRA124_CLK_AUDIO2_MUX 302
#define TEGRA124_CLK_AUDIO3_MUX 303
#define TEGRA124_CLK_AUDIO4_MUX 304
#define TEGRA124_CLK_SPDIF_MUX 305
#define TEGRA124_CLK_CLK_OUT_1_MUX 306
#define TEGRA124_CLK_CLK_OUT_2_MUX 307
#define TEGRA124_CLK_CLK_OUT_3_MUX 308
#define TEGRA124_CLK_DSIA_MUX 309
#define TEGRA124_CLK_DSIB_MUX 310
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_PLL_M_UD 311
#define TEGRA124_CLK_CLK_MAX 312
#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
arch/arm/dts/include/dt-bindings/clock/tegra20-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra20-car.
*
* The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 95 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 96 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
#define TEGRA20_CLK_CPU 0
/* 1 */
/* 2 */
#define TEGRA20_CLK_AC97 3
#define TEGRA20_CLK_RTC 4
#define TEGRA20_CLK_TIMER 5
#define TEGRA20_CLK_UARTA 6
/* 7 (register bit affects uart2 and vfir) */
#define TEGRA20_CLK_GPIO 8
#define TEGRA20_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA20_CLK_I2S1 11
#define TEGRA20_CLK_I2C1 12
#define TEGRA20_CLK_NDFLASH 13
#define TEGRA20_CLK_SDMMC1 14
#define TEGRA20_CLK_SDMMC4 15
#define TEGRA20_CLK_TWC 16
#define TEGRA20_CLK_PWM 17
#define TEGRA20_CLK_I2S2 18
#define TEGRA20_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA20_CLK_GR2D 21
#define TEGRA20_CLK_USBD 22
#define TEGRA20_CLK_ISP 23
#define TEGRA20_CLK_GR3D 24
#define TEGRA20_CLK_IDE 25
#define TEGRA20_CLK_DISP2 26
#define TEGRA20_CLK_DISP1 27
#define TEGRA20_CLK_HOST1X 28
#define TEGRA20_CLK_VCP 29
/* 30 */
#define TEGRA20_CLK_CACHE2 31
#define TEGRA20_CLK_MEM 32
#define TEGRA20_CLK_AHBDMA 33
#define TEGRA20_CLK_APBDMA 34
/* 35 */
#define TEGRA20_CLK_KBC 36
#define TEGRA20_CLK_STAT_MON 37
#define TEGRA20_CLK_PMC 38
#define TEGRA20_CLK_FUSE 39
#define TEGRA20_CLK_KFUSE 40
#define TEGRA20_CLK_SBC1 41
#define TEGRA20_CLK_NOR 42
#define TEGRA20_CLK_SPI 43
#define TEGRA20_CLK_SBC2 44
#define TEGRA20_CLK_XIO 45
#define TEGRA20_CLK_SBC3 46
#define TEGRA20_CLK_DVC 47
#define TEGRA20_CLK_DSI 48
/* 49 (register bit affects tvo and cve) */
#define TEGRA20_CLK_MIPI 50
#define TEGRA20_CLK_HDMI 51
#define TEGRA20_CLK_CSI 52
#define TEGRA20_CLK_TVDAC 53
#define TEGRA20_CLK_I2C2 54
#define TEGRA20_CLK_UARTC 55
/* 56 */
#define TEGRA20_CLK_EMC 57
#define TEGRA20_CLK_USB2 58
#define TEGRA20_CLK_USB3 59
#define TEGRA20_CLK_MPE 60
#define TEGRA20_CLK_VDE 61
#define TEGRA20_CLK_BSEA 62
#define TEGRA20_CLK_BSEV 63
#define TEGRA20_CLK_SPEEDO 64
#define TEGRA20_CLK_UARTD 65
#define TEGRA20_CLK_UARTE 66
#define TEGRA20_CLK_I2C3 67
#define TEGRA20_CLK_SBC4 68
#define TEGRA20_CLK_SDMMC3 69
#define TEGRA20_CLK_PEX 70
#define TEGRA20_CLK_OWR 71
#define TEGRA20_CLK_AFI 72
#define TEGRA20_CLK_CSITE 73
/* 74 */
#define TEGRA20_CLK_AVPUCQ 75
#define TEGRA20_CLK_LA 76
/* 77 */
/* 78 */
/* 79 */
/* 80 */
/* 81 */
/* 82 */
/* 83 */
#define TEGRA20_CLK_IRAMA 84
#define TEGRA20_CLK_IRAMB 85
#define TEGRA20_CLK_IRAMC 86
#define TEGRA20_CLK_IRAMD 87
#define TEGRA20_CLK_CRAM2 88
#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
#define TEGRA20_CLK_CLK_D 90
/* 91 */
#define TEGRA20_CLK_CSUS 92
#define TEGRA20_CLK_CDEV2 93
#define TEGRA20_CLK_CDEV1 94
/* 95 */
#define TEGRA20_CLK_UARTB 96
#define TEGRA20_CLK_VFIR 97
#define TEGRA20_CLK_SPDIF_IN 98
#define TEGRA20_CLK_SPDIF_OUT 99
#define TEGRA20_CLK_VI 100
#define TEGRA20_CLK_VI_SENSOR 101
#define TEGRA20_CLK_TVO 102
#define TEGRA20_CLK_CVE 103
#define TEGRA20_CLK_OSC 104
#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
#define TEGRA20_CLK_CLK_M 106
#define TEGRA20_CLK_SCLK 107
#define TEGRA20_CLK_CCLK 108
#define TEGRA20_CLK_HCLK 109
#define TEGRA20_CLK_PCLK 110
#define TEGRA20_CLK_BLINK 111
#define TEGRA20_CLK_PLL_A 112
#define TEGRA20_CLK_PLL_A_OUT0 113
#define TEGRA20_CLK_PLL_C 114
#define TEGRA20_CLK_PLL_C_OUT1 115
#define TEGRA20_CLK_PLL_D 116
#define TEGRA20_CLK_PLL_D_OUT0 117
#define TEGRA20_CLK_PLL_E 118
#define TEGRA20_CLK_PLL_M 119
#define TEGRA20_CLK_PLL_M_OUT1 120
#define TEGRA20_CLK_PLL_P 121
#define TEGRA20_CLK_PLL_P_OUT1 122
#define TEGRA20_CLK_PLL_P_OUT2 123
#define TEGRA20_CLK_PLL_P_OUT3 124
#define TEGRA20_CLK_PLL_P_OUT4 125
#define TEGRA20_CLK_PLL_S 126
#define TEGRA20_CLK_PLL_U 127
#define TEGRA20_CLK_PLL_X 128
#define TEGRA20_CLK_COP 129 /* a/k/a avp */
#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
#define TEGRA20_CLK_PLL_REF 131
#define TEGRA20_CLK_TWD 132
#define TEGRA20_CLK_CLK_MAX 133
#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
arch/arm/dts/include/dt-bindings/clock/tegra30-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra30-car.
*
* The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 160 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
#define TEGRA30_CLK_CPU 0
/* 1 */
/* 2 */
/* 3 */
#define TEGRA30_CLK_RTC 4
#define TEGRA30_CLK_TIMER 5
#define TEGRA30_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
#define TEGRA30_CLK_GPIO 8
#define TEGRA30_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA30_CLK_I2S1 11
#define TEGRA30_CLK_I2C1 12
#define TEGRA30_CLK_NDFLASH 13
#define TEGRA30_CLK_SDMMC1 14
#define TEGRA30_CLK_SDMMC4 15
/* 16 */
#define TEGRA30_CLK_PWM 17
#define TEGRA30_CLK_I2S2 18
#define TEGRA30_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA30_CLK_GR2D 21
#define TEGRA30_CLK_USBD 22
#define TEGRA30_CLK_ISP 23
#define TEGRA30_CLK_GR3D 24
/* 25 */
#define TEGRA30_CLK_DISP2 26
#define TEGRA30_CLK_DISP1 27
#define TEGRA30_CLK_HOST1X 28
#define TEGRA30_CLK_VCP 29
#define TEGRA30_CLK_I2S0 30
#define TEGRA30_CLK_COP_CACHE 31
#define TEGRA30_CLK_MC 32
#define TEGRA30_CLK_AHBDMA 33
#define TEGRA30_CLK_APBDMA 34
/* 35 */
#define TEGRA30_CLK_KBC 36
#define TEGRA30_CLK_STATMON 37
#define TEGRA30_CLK_PMC 38
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA30_CLK_KFUSE 40
#define TEGRA30_CLK_SBC1 41
#define TEGRA30_CLK_NOR 42
/* 43 */
#define TEGRA30_CLK_SBC2 44
/* 45 */
#define TEGRA30_CLK_SBC3 46
#define TEGRA30_CLK_I2C5 47
#define TEGRA30_CLK_DSIA 48
/* 49 (register bit affects cve and tvo) */
#define TEGRA30_CLK_MIPI 50
#define TEGRA30_CLK_HDMI 51
#define TEGRA30_CLK_CSI 52
#define TEGRA30_CLK_TVDAC 53
#define TEGRA30_CLK_I2C2 54
#define TEGRA30_CLK_UARTC 55
/* 56 */
#define TEGRA30_CLK_EMC 57
#define TEGRA30_CLK_USB2 58
#define TEGRA30_CLK_USB3 59
#define TEGRA30_CLK_MPE 60
#define TEGRA30_CLK_VDE 61
#define TEGRA30_CLK_BSEA 62
#define TEGRA30_CLK_BSEV 63
#define TEGRA30_CLK_SPEEDO 64
#define TEGRA30_CLK_UARTD 65
#define TEGRA30_CLK_UARTE 66
#define TEGRA30_CLK_I2C3 67
#define TEGRA30_CLK_SBC4 68
#define TEGRA30_CLK_SDMMC3 69
#define TEGRA30_CLK_PCIE 70
#define TEGRA30_CLK_OWR 71
#define TEGRA30_CLK_AFI 72
#define TEGRA30_CLK_CSITE 73
/* 74 */
#define TEGRA30_CLK_AVPUCQ 75
#define TEGRA30_CLK_LA 76
/* 77 */
/* 78 */
#define TEGRA30_CLK_DTV 79
#define TEGRA30_CLK_NDSPEED 80
#define TEGRA30_CLK_I2CSLOW 81
#define TEGRA30_CLK_DSIB 82
/* 83 */
#define TEGRA30_CLK_IRAMA 84
#define TEGRA30_CLK_IRAMB 85
#define TEGRA30_CLK_IRAMC 86
#define TEGRA30_CLK_IRAMD 87
#define TEGRA30_CLK_CRAM2 88
/* 89 */
#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
/* 91 */
#define TEGRA30_CLK_CSUS 92
#define TEGRA30_CLK_CDEV2 93
#define TEGRA30_CLK_CDEV1 94
/* 95 */
#define TEGRA30_CLK_CPU_G 96
#define TEGRA30_CLK_CPU_LP 97
#define TEGRA30_CLK_GR3D2 98
#define TEGRA30_CLK_MSELECT 99
#define TEGRA30_CLK_TSENSOR 100
#define TEGRA30_CLK_I2S3 101
#define TEGRA30_CLK_I2S4 102
#define TEGRA30_CLK_I2C4 103
#define TEGRA30_CLK_SBC5 104
#define TEGRA30_CLK_SBC6 105
#define TEGRA30_CLK_D_AUDIO 106
#define TEGRA30_CLK_APBIF 107
#define TEGRA30_CLK_DAM0 108
#define TEGRA30_CLK_DAM1 109
#define TEGRA30_CLK_DAM2 110
#define TEGRA30_CLK_HDA2CODEC_2X 111
#define TEGRA30_CLK_ATOMICS 112
#define TEGRA30_CLK_AUDIO0_2X 113
#define TEGRA30_CLK_AUDIO1_2X 114
#define TEGRA30_CLK_AUDIO2_2X 115
#define TEGRA30_CLK_AUDIO3_2X 116
#define TEGRA30_CLK_AUDIO4_2X 117
#define TEGRA30_CLK_SPDIF_2X 118
#define TEGRA30_CLK_ACTMON 119
#define TEGRA30_CLK_EXTERN1 120
#define TEGRA30_CLK_EXTERN2 121
#define TEGRA30_CLK_EXTERN3 122
#define TEGRA30_CLK_SATA_OOB 123
#define TEGRA30_CLK_SATA 124
#define TEGRA30_CLK_HDA 125
/* 126 */
#define TEGRA30_CLK_SE 127
#define TEGRA30_CLK_HDA2HDMI 128
#define TEGRA30_CLK_SATA_COLD 129
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 */
/* 144 */
/* 145 */
/* 146 */
/* 147 */
/* 148 */
/* 149 */
/* 150 */
/* 151 */
/* 152 */
/* 153 */
/* 154 */
/* 155 */
/* 156 */
/* 157 */
/* 158 */
/* 159 */
#define TEGRA30_CLK_UARTB 160
#define TEGRA30_CLK_VFIR 161
#define TEGRA30_CLK_SPDIF_IN 162
#define TEGRA30_CLK_SPDIF_OUT 163
#define TEGRA30_CLK_VI 164
#define TEGRA30_CLK_VI_SENSOR 165
#define TEGRA30_CLK_FUSE 166
#define TEGRA30_CLK_FUSE_BURN 167
#define TEGRA30_CLK_CVE 168
#define TEGRA30_CLK_TVO 169
#define TEGRA30_CLK_CLK_32K 170
#define TEGRA30_CLK_CLK_M 171
#define TEGRA30_CLK_CLK_M_DIV2 172
#define TEGRA30_CLK_CLK_M_DIV4 173
#define TEGRA30_CLK_PLL_REF 174
#define TEGRA30_CLK_PLL_C 175
#define TEGRA30_CLK_PLL_C_OUT1 176
#define TEGRA30_CLK_PLL_M 177
#define TEGRA30_CLK_PLL_M_OUT1 178
#define TEGRA30_CLK_PLL_P 179
#define TEGRA30_CLK_PLL_P_OUT1 180
#define TEGRA30_CLK_PLL_P_OUT2 181
#define TEGRA30_CLK_PLL_P_OUT3 182
#define TEGRA30_CLK_PLL_P_OUT4 183
#define TEGRA30_CLK_PLL_A 184
#define TEGRA30_CLK_PLL_A_OUT0 185
#define TEGRA30_CLK_PLL_D 186
#define TEGRA30_CLK_PLL_D_OUT0 187
#define TEGRA30_CLK_PLL_D2 188
#define TEGRA30_CLK_PLL_D2_OUT0 189
#define TEGRA30_CLK_PLL_U 190
#define TEGRA30_CLK_PLL_X 191
#define TEGRA30_CLK_PLL_X_OUT0 192
#define TEGRA30_CLK_PLL_E 193
#define TEGRA30_CLK_SPDIF_IN_SYNC 194
#define TEGRA30_CLK_I2S0_SYNC 195
#define TEGRA30_CLK_I2S1_SYNC 196
#define TEGRA30_CLK_I2S2_SYNC 197
#define TEGRA30_CLK_I2S3_SYNC 198
#define TEGRA30_CLK_I2S4_SYNC 199
#define TEGRA30_CLK_VIMCLK_SYNC 200
#define TEGRA30_CLK_AUDIO0 201
#define TEGRA30_CLK_AUDIO1 202
#define TEGRA30_CLK_AUDIO2 203
#define TEGRA30_CLK_AUDIO3 204
#define TEGRA30_CLK_AUDIO4 205
#define TEGRA30_CLK_SPDIF 206
#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
#define TEGRA30_CLK_SCLK 210
#define TEGRA30_CLK_BLINK 211
#define TEGRA30_CLK_CCLK_G 212
#define TEGRA30_CLK_CCLK_LP 213
#define TEGRA30_CLK_TWD 214
#define TEGRA30_CLK_CML0 215
#define TEGRA30_CLK_CML1 216
#define TEGRA30_CLK_HCLK 217
#define TEGRA30_CLK_PCLK 218
/* 219 */
/* 220 */
/* 221 */
/* 222 */
/* 223 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA30_CLK_CLK_OUT_1_MUX 300
#define TEGRA30_CLK_CLK_OUT_2_MUX 301
#define TEGRA30_CLK_CLK_OUT_3_MUX 302
#define TEGRA30_CLK_AUDIO0_MUX 303
#define TEGRA30_CLK_AUDIO1_MUX 304
#define TEGRA30_CLK_AUDIO2_MUX 305
#define TEGRA30_CLK_AUDIO3_MUX 306
#define TEGRA30_CLK_AUDIO4_MUX 307
#define TEGRA30_CLK_SPDIF_MUX 308
#define TEGRA30_CLK_CLK_MAX 309
#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
arch/arm/dts/include/dt-bindings/gpio/gpio.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for most GPIO bindings.
*
* Most GPIO bindings include a flags cell as part of the GPIO specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_GPIO_GPIO_H
#define _DT_BINDINGS_GPIO_GPIO_H
#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1
#endif
arch/arm/dts/include/dt-bindings/gpio/tegra-gpio.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra*-gpio.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#include <dt-bindings/gpio/gpio.h>
#define TEGRA_GPIO_BANK_ID_A 0
#define TEGRA_GPIO_BANK_ID_B 1
#define TEGRA_GPIO_BANK_ID_C 2
#define TEGRA_GPIO_BANK_ID_D 3
#define TEGRA_GPIO_BANK_ID_E 4
#define TEGRA_GPIO_BANK_ID_F 5
#define TEGRA_GPIO_BANK_ID_G 6
#define TEGRA_GPIO_BANK_ID_H 7
#define TEGRA_GPIO_BANK_ID_I 8
#define TEGRA_GPIO_BANK_ID_J 9
#define TEGRA_GPIO_BANK_ID_K 10
#define TEGRA_GPIO_BANK_ID_L 11
#define TEGRA_GPIO_BANK_ID_M 12
#define TEGRA_GPIO_BANK_ID_N 13
#define TEGRA_GPIO_BANK_ID_O 14
#define TEGRA_GPIO_BANK_ID_P 15
#define TEGRA_GPIO_BANK_ID_Q 16
#define TEGRA_GPIO_BANK_ID_R 17
#define TEGRA_GPIO_BANK_ID_S 18
#define TEGRA_GPIO_BANK_ID_T 19
#define TEGRA_GPIO_BANK_ID_U 20
#define TEGRA_GPIO_BANK_ID_V 21
#define TEGRA_GPIO_BANK_ID_W 22
#define TEGRA_GPIO_BANK_ID_X 23
#define TEGRA_GPIO_BANK_ID_Y 24
#define TEGRA_GPIO_BANK_ID_Z 25
#define TEGRA_GPIO_BANK_ID_AA 26
#define TEGRA_GPIO_BANK_ID_BB 27
#define TEGRA_GPIO_BANK_ID_CC 28
#define TEGRA_GPIO_BANK_ID_DD 29
#define TEGRA_GPIO_BANK_ID_EE 30
#define TEGRA_GPIO_BANK_ID_FF 31
#define TEGRA_GPIO(bank, offset) \
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
#endif
arch/arm/dts/include/dt-bindings/interrupt-controller/arm-gic.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for the ARM GIC.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
#include <dt-bindings/interrupt-controller/irq.h>
/* interrupt specific cell 0 */
#define GIC_SPI 0
#define GIC_PPI 1
/*
* Interrupt specifier cell 2.
* The flaggs in irq.h are valid, plus those below.
*/
#define GIC_CPU_MASK_RAW(x) ((x) << 8)
#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
#endif
arch/arm/dts/include/dt-bindings/interrupt-controller/irq.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for most IRQ bindings.
*
* Most IRQ bindings include a flags cell as part of the IRQ specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define IRQ_TYPE_NONE 0
#define IRQ_TYPE_EDGE_RISING 1
#define IRQ_TYPE_EDGE_FALLING 2
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
#endif
arch/microblaze/dts/include/dt-bindings 0 → 120000
View file @ d1bdfe37
../../../../include/dt-bindings
\ No newline at end of file
arch/microblaze/dts/include/dt-bindings/clock/tegra114-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra114-car.
*
* The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 160 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
/* 0 */
/* 1 */
/* 2 */
/* 3 */
#define TEGRA114_CLK_RTC 4
#define TEGRA114_CLK_TIMER 5
#define TEGRA114_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA114_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA114_CLK_I2S1 11
#define TEGRA114_CLK_I2C1 12
#define TEGRA114_CLK_NDFLASH 13
#define TEGRA114_CLK_SDMMC1 14
#define TEGRA114_CLK_SDMMC4 15
/* 16 */
#define TEGRA114_CLK_PWM 17
#define TEGRA114_CLK_I2S2 18
#define TEGRA114_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA114_CLK_GR2D 21
#define TEGRA114_CLK_USBD 22
#define TEGRA114_CLK_ISP 23
#define TEGRA114_CLK_GR3D 24
/* 25 */
#define TEGRA114_CLK_DISP2 26
#define TEGRA114_CLK_DISP1 27
#define TEGRA114_CLK_HOST1X 28
#define TEGRA114_CLK_VCP 29
#define TEGRA114_CLK_I2S0 30
/* 31 */
/* 32 */
/* 33 */
#define TEGRA114_CLK_APBDMA 34
/* 35 */
#define TEGRA114_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA114_CLK_KFUSE 40
#define TEGRA114_CLK_SBC1 41
#define TEGRA114_CLK_NOR 42
/* 43 */
#define TEGRA114_CLK_SBC2 44
/* 45 */
#define TEGRA114_CLK_SBC3 46
#define TEGRA114_CLK_I2C5 47
#define TEGRA114_CLK_DSIA 48
/* 49 */
#define TEGRA114_CLK_MIPI 50
#define TEGRA114_CLK_HDMI 51
#define TEGRA114_CLK_CSI 52
/* 53 */
#define TEGRA114_CLK_I2C2 54
#define TEGRA114_CLK_UARTC 55
#define TEGRA114_CLK_MIPI_CAL 56
#define TEGRA114_CLK_EMC 57
#define TEGRA114_CLK_USB2 58
#define TEGRA114_CLK_USB3 59
/* 60 */
#define TEGRA114_CLK_VDE 61
#define TEGRA114_CLK_BSEA 62
#define TEGRA114_CLK_BSEV 63
/* 64 */
#define TEGRA114_CLK_UARTD 65
/* 66 */
#define TEGRA114_CLK_I2C3 67
#define TEGRA114_CLK_SBC4 68
#define TEGRA114_CLK_SDMMC3 69
/* 70 */
#define TEGRA114_CLK_OWR 71
/* 72 */
#define TEGRA114_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA114_CLK_LA 76
#define TEGRA114_CLK_TRACE 77
#define TEGRA114_CLK_SOC_THERM 78
#define TEGRA114_CLK_DTV 79
#define TEGRA114_CLK_NDSPEED 80
#define TEGRA114_CLK_I2CSLOW 81
#define TEGRA114_CLK_DSIB 82
#define TEGRA114_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA114_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA114_CLK_MSENC 91
#define TEGRA114_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA114_CLK_MSELECT 99
#define TEGRA114_CLK_TSENSOR 100
#define TEGRA114_CLK_I2S3 101
#define TEGRA114_CLK_I2S4 102
#define TEGRA114_CLK_I2C4 103
#define TEGRA114_CLK_SBC5 104
#define TEGRA114_CLK_SBC6 105
#define TEGRA114_CLK_D_AUDIO 106
#define TEGRA114_CLK_APBIF 107
#define TEGRA114_CLK_DAM0 108
#define TEGRA114_CLK_DAM1 109
#define TEGRA114_CLK_DAM2 110
#define TEGRA114_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA114_CLK_AUDIO0_2X 113
#define TEGRA114_CLK_AUDIO1_2X 114
#define TEGRA114_CLK_AUDIO2_2X 115
#define TEGRA114_CLK_AUDIO3_2X 116
#define TEGRA114_CLK_AUDIO4_2X 117
#define TEGRA114_CLK_SPDIF_2X 118
#define TEGRA114_CLK_ACTMON 119
#define TEGRA114_CLK_EXTERN1 120
#define TEGRA114_CLK_EXTERN2 121
#define TEGRA114_CLK_EXTERN3 122
/* 123 */
/* 124 */
#define TEGRA114_CLK_HDA 125
/* 126 */
#define TEGRA114_CLK_SE 127
#define TEGRA114_CLK_HDA2HDMI 128
/* 129 */
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA114_CLK_CILAB 144
#define TEGRA114_CLK_CILCD 145
#define TEGRA114_CLK_CILE 146
#define TEGRA114_CLK_DSIALP 147
#define TEGRA114_CLK_DSIBLP 148
/* 149 */
#define TEGRA114_CLK_DDS 150
/* 151 */
#define TEGRA114_CLK_DP2 152
#define TEGRA114_CLK_AMX 153
#define TEGRA114_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA114_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
/* 166 */
/* 167 */
/* 168 */
/* 169 */
/* 170 */
/* 171 */
/* 172 */
/* 173 */
/* 174 */
/* 175 */
/* 176 */
/* 177 */
/* 178 */
/* 179 */
/* 180 */
/* 181 */
/* 182 */
/* 183 */
/* 184 */
/* 185 */
/* 186 */
/* 187 */
/* 188 */
/* 189 */
/* 190 */
/* 191 */
#define TEGRA114_CLK_UARTB 192
#define TEGRA114_CLK_VFIR 193
#define TEGRA114_CLK_SPDIF_IN 194
#define TEGRA114_CLK_SPDIF_OUT 195
#define TEGRA114_CLK_VI 196
#define TEGRA114_CLK_VI_SENSOR 197
#define TEGRA114_CLK_FUSE 198
#define TEGRA114_CLK_FUSE_BURN 199
#define TEGRA114_CLK_CLK_32K 200
#define TEGRA114_CLK_CLK_M 201
#define TEGRA114_CLK_CLK_M_DIV2 202
#define TEGRA114_CLK_CLK_M_DIV4 203
#define TEGRA114_CLK_PLL_REF 204
#define TEGRA114_CLK_PLL_C 205
#define TEGRA114_CLK_PLL_C_OUT1 206
#define TEGRA114_CLK_PLL_C2 207
#define TEGRA114_CLK_PLL_C3 208
#define TEGRA114_CLK_PLL_M 209
#define TEGRA114_CLK_PLL_M_OUT1 210
#define TEGRA114_CLK_PLL_P 211
#define TEGRA114_CLK_PLL_P_OUT1 212
#define TEGRA114_CLK_PLL_P_OUT2 213
#define TEGRA114_CLK_PLL_P_OUT3 214
#define TEGRA114_CLK_PLL_P_OUT4 215
#define TEGRA114_CLK_PLL_A 216
#define TEGRA114_CLK_PLL_A_OUT0 217
#define TEGRA114_CLK_PLL_D 218
#define TEGRA114_CLK_PLL_D_OUT0 219
#define TEGRA114_CLK_PLL_D2 220
#define TEGRA114_CLK_PLL_D2_OUT0 221
#define TEGRA114_CLK_PLL_U 222
#define TEGRA114_CLK_PLL_U_480M 223
#define TEGRA114_CLK_PLL_U_60M 224
#define TEGRA114_CLK_PLL_U_48M 225
#define TEGRA114_CLK_PLL_U_12M 226
#define TEGRA114_CLK_PLL_X 227
#define TEGRA114_CLK_PLL_X_OUT0 228
#define TEGRA114_CLK_PLL_RE_VCO 229
#define TEGRA114_CLK_PLL_RE_OUT 230
#define TEGRA114_CLK_PLL_E_OUT0 231
#define TEGRA114_CLK_SPDIF_IN_SYNC 232
#define TEGRA114_CLK_I2S0_SYNC 233
#define TEGRA114_CLK_I2S1_SYNC 234
#define TEGRA114_CLK_I2S2_SYNC 235
#define TEGRA114_CLK_I2S3_SYNC 236
#define TEGRA114_CLK_I2S4_SYNC 237
#define TEGRA114_CLK_VIMCLK_SYNC 238
#define TEGRA114_CLK_AUDIO0 239
#define TEGRA114_CLK_AUDIO1 240
#define TEGRA114_CLK_AUDIO2 241
#define TEGRA114_CLK_AUDIO3 242
#define TEGRA114_CLK_AUDIO4 243
#define TEGRA114_CLK_SPDIF 244
#define TEGRA114_CLK_CLK_OUT_1 245
#define TEGRA114_CLK_CLK_OUT_2 246
#define TEGRA114_CLK_CLK_OUT_3 247
#define TEGRA114_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA114_CLK_XUSB_HOST_SRC 252
#define TEGRA114_CLK_XUSB_FALCON_SRC 253
#define TEGRA114_CLK_XUSB_FS_SRC 254
#define TEGRA114_CLK_XUSB_SS_SRC 255
#define TEGRA114_CLK_XUSB_DEV_SRC 256
#define TEGRA114_CLK_XUSB_DEV 257
#define TEGRA114_CLK_XUSB_HS_SRC 258
#define TEGRA114_CLK_SCLK 259
#define TEGRA114_CLK_HCLK 260
#define TEGRA114_CLK_PCLK 261
#define TEGRA114_CLK_CCLK_G 262
#define TEGRA114_CLK_CCLK_LP 263
#define TEGRA114_CLK_DFLL_REF 264
#define TEGRA114_CLK_DFLL_SOC 265
/* 266 */
/* 267 */
/* 268 */
/* 269 */
/* 270 */
/* 271 */
/* 272 */
/* 273 */
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA114_CLK_AUDIO0_MUX 300
#define TEGRA114_CLK_AUDIO1_MUX 301
#define TEGRA114_CLK_AUDIO2_MUX 302
#define TEGRA114_CLK_AUDIO3_MUX 303
#define TEGRA114_CLK_AUDIO4_MUX 304
#define TEGRA114_CLK_SPDIF_MUX 305
#define TEGRA114_CLK_CLK_OUT_1_MUX 306
#define TEGRA114_CLK_CLK_OUT_2_MUX 307
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_CLK_MAX 311
#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
arch/microblaze/dts/include/dt-bindings/clock/tegra124-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra124-car.
*
* The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 185 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 185 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
/* 0 */
/* 1 */
/* 2 */
#define TEGRA124_CLK_ISPB 3
#define TEGRA124_CLK_RTC 4
#define TEGRA124_CLK_TIMER 5
#define TEGRA124_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA124_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA124_CLK_I2S1 11
#define TEGRA124_CLK_I2C1 12
#define TEGRA124_CLK_NDFLASH 13
#define TEGRA124_CLK_SDMMC1 14
#define TEGRA124_CLK_SDMMC4 15
/* 16 */
#define TEGRA124_CLK_PWM 17
#define TEGRA124_CLK_I2S2 18
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA124_CLK_USBD 22
#define TEGRA124_CLK_ISP 23
/* 26 */
/* 25 */
#define TEGRA124_CLK_DISP2 26
#define TEGRA124_CLK_DISP1 27
#define TEGRA124_CLK_HOST1X 28
#define TEGRA124_CLK_VCP 29
#define TEGRA124_CLK_I2S0 30
/* 31 */
/* 32 */
/* 33 */
#define TEGRA124_CLK_APBDMA 34
/* 35 */
#define TEGRA124_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA124_CLK_KFUSE 40
#define TEGRA124_CLK_SBC1 41
#define TEGRA124_CLK_NOR 42
/* 43 */
#define TEGRA124_CLK_SBC2 44
/* 45 */
#define TEGRA124_CLK_SBC3 46
#define TEGRA124_CLK_I2C5 47
#define TEGRA124_CLK_DSIA 48
/* 49 */
#define TEGRA124_CLK_MIPI 50
#define TEGRA124_CLK_HDMI 51
#define TEGRA124_CLK_CSI 52
/* 53 */
#define TEGRA124_CLK_I2C2 54
#define TEGRA124_CLK_UARTC 55
#define TEGRA124_CLK_MIPI_CAL 56
#define TEGRA124_CLK_EMC 57
#define TEGRA124_CLK_USB2 58
#define TEGRA124_CLK_USB3 59
/* 60 */
#define TEGRA124_CLK_VDE 61
#define TEGRA124_CLK_BSEA 62
#define TEGRA124_CLK_BSEV 63
/* 64 */
#define TEGRA124_CLK_UARTD 65
#define TEGRA124_CLK_UARTE 66
#define TEGRA124_CLK_I2C3 67
#define TEGRA124_CLK_SBC4 68
#define TEGRA124_CLK_SDMMC3 69
#define TEGRA124_CLK_PCIE 70
#define TEGRA124_CLK_OWR 71
#define TEGRA124_CLK_AFI 72
#define TEGRA124_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA124_CLK_LA 76
#define TEGRA124_CLK_TRACE 77
#define TEGRA124_CLK_SOC_THERM 78
#define TEGRA124_CLK_DTV 79
#define TEGRA124_CLK_NDSPEED 80
#define TEGRA124_CLK_I2CSLOW 81
#define TEGRA124_CLK_DSIB 82
#define TEGRA124_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA124_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA124_CLK_MSENC 91
#define TEGRA124_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA124_CLK_MSELECT 99
#define TEGRA124_CLK_TSENSOR 100
#define TEGRA124_CLK_I2S3 101
#define TEGRA124_CLK_I2S4 102
#define TEGRA124_CLK_I2C4 103
#define TEGRA124_CLK_SBC5 104
#define TEGRA124_CLK_SBC6 105
#define TEGRA124_CLK_D_AUDIO 106
#define TEGRA124_CLK_APBIF 107
#define TEGRA124_CLK_DAM0 108
#define TEGRA124_CLK_DAM1 109
#define TEGRA124_CLK_DAM2 110
#define TEGRA124_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA124_CLK_AUDIO0_2X 113
#define TEGRA124_CLK_AUDIO1_2X 114
#define TEGRA124_CLK_AUDIO2_2X 115
#define TEGRA124_CLK_AUDIO3_2X 116
#define TEGRA124_CLK_AUDIO4_2X 117
#define TEGRA124_CLK_SPDIF_2X 118
#define TEGRA124_CLK_ACTMON 119
#define TEGRA124_CLK_EXTERN1 120
#define TEGRA124_CLK_EXTERN2 121
#define TEGRA124_CLK_EXTERN3 122
#define TEGRA124_CLK_SATA_OOB 123
#define TEGRA124_CLK_SATA 124
#define TEGRA124_CLK_HDA 125
/* 126 */
#define TEGRA124_CLK_SE 127
#define TEGRA124_CLK_HDA2HDMI 128
#define TEGRA124_CLK_SATA_COLD 129
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA124_CLK_CILAB 144
#define TEGRA124_CLK_CILCD 145
#define TEGRA124_CLK_CILE 146
#define TEGRA124_CLK_DSIALP 147
#define TEGRA124_CLK_DSIBLP 148
#define TEGRA124_CLK_ENTROPY 149
#define TEGRA124_CLK_DDS 150
/* 151 */
#define TEGRA124_CLK_DP2 152
#define TEGRA124_CLK_AMX 153
#define TEGRA124_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA124_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
#define TEGRA124_CLK_I2C6 166
/* 167 */
/* 168 */
/* 169 */
/* 170 */
#define TEGRA124_CLK_VIM2_CLK 171
/* 172 */
/* 173 */
/* 174 */
/* 175 */
#define TEGRA124_CLK_HDMI_AUDIO 176
#define TEGRA124_CLK_CLK72MHZ 177
#define TEGRA124_CLK_VIC03 178
/* 179 */
#define TEGRA124_CLK_ADX1 180
#define TEGRA124_CLK_DPAUX 181
#define TEGRA124_CLK_SOR0 182
/* 183 */
#define TEGRA124_CLK_GPU 184
#define TEGRA124_CLK_AMX1 185
#define TEGRA124_CLK_AFC0 186
#define TEGRA124_CLK_AFC1 187
#define TEGRA124_CLK_AFC2 188
#define TEGRA124_CLK_AFC3 189
#define TEGRA124_CLK_AFC4 190
#define TEGRA124_CLK_AFC5 191
#define TEGRA124_CLK_UARTB 192
#define TEGRA124_CLK_VFIR 193
#define TEGRA124_CLK_SPDIF_IN 194
#define TEGRA124_CLK_SPDIF_OUT 195
#define TEGRA124_CLK_VI 196
#define TEGRA124_CLK_VI_SENSOR 197
#define TEGRA124_CLK_FUSE 198
#define TEGRA124_CLK_FUSE_BURN 199
#define TEGRA124_CLK_CLK_32K 200
#define TEGRA124_CLK_CLK_M 201
#define TEGRA124_CLK_CLK_M_DIV2 202
#define TEGRA124_CLK_CLK_M_DIV4 203
#define TEGRA124_CLK_PLL_REF 204
#define TEGRA124_CLK_PLL_C 205
#define TEGRA124_CLK_PLL_C_OUT1 206
#define TEGRA124_CLK_PLL_C2 207
#define TEGRA124_CLK_PLL_C3 208
#define TEGRA124_CLK_PLL_M 209
#define TEGRA124_CLK_PLL_M_OUT1 210
#define TEGRA124_CLK_PLL_P 211
#define TEGRA124_CLK_PLL_P_OUT1 212
#define TEGRA124_CLK_PLL_P_OUT2 213
#define TEGRA124_CLK_PLL_P_OUT3 214
#define TEGRA124_CLK_PLL_P_OUT4 215
#define TEGRA124_CLK_PLL_A 216
#define TEGRA124_CLK_PLL_A_OUT0 217
#define TEGRA124_CLK_PLL_D 218
#define TEGRA124_CLK_PLL_D_OUT0 219
#define TEGRA124_CLK_PLL_D2 220
#define TEGRA124_CLK_PLL_D2_OUT0 221
#define TEGRA124_CLK_PLL_U 222
#define TEGRA124_CLK_PLL_U_480M 223
#define TEGRA124_CLK_PLL_U_60M 224
#define TEGRA124_CLK_PLL_U_48M 225
#define TEGRA124_CLK_PLL_U_12M 226
#define TEGRA124_CLK_PLL_X 227
#define TEGRA124_CLK_PLL_X_OUT0 228
#define TEGRA124_CLK_PLL_RE_VCO 229
#define TEGRA124_CLK_PLL_RE_OUT 230
#define TEGRA124_CLK_PLL_E 231
#define TEGRA124_CLK_SPDIF_IN_SYNC 232
#define TEGRA124_CLK_I2S0_SYNC 233
#define TEGRA124_CLK_I2S1_SYNC 234
#define TEGRA124_CLK_I2S2_SYNC 235
#define TEGRA124_CLK_I2S3_SYNC 236
#define TEGRA124_CLK_I2S4_SYNC 237
#define TEGRA124_CLK_VIMCLK_SYNC 238
#define TEGRA124_CLK_AUDIO0 239
#define TEGRA124_CLK_AUDIO1 240
#define TEGRA124_CLK_AUDIO2 241
#define TEGRA124_CLK_AUDIO3 242
#define TEGRA124_CLK_AUDIO4 243
#define TEGRA124_CLK_SPDIF 244
#define TEGRA124_CLK_CLK_OUT_1 245
#define TEGRA124_CLK_CLK_OUT_2 246
#define TEGRA124_CLK_CLK_OUT_3 247
#define TEGRA124_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA124_CLK_XUSB_HOST_SRC 252
#define TEGRA124_CLK_XUSB_FALCON_SRC 253
#define TEGRA124_CLK_XUSB_FS_SRC 254
#define TEGRA124_CLK_XUSB_SS_SRC 255
#define TEGRA124_CLK_XUSB_DEV_SRC 256
#define TEGRA124_CLK_XUSB_DEV 257
#define TEGRA124_CLK_XUSB_HS_SRC 258
#define TEGRA124_CLK_SCLK 259
#define TEGRA124_CLK_HCLK 260
#define TEGRA124_CLK_PCLK 261
#define TEGRA124_CLK_CCLK_G 262
#define TEGRA124_CLK_CCLK_LP 263
#define TEGRA124_CLK_DFLL_REF 264
#define TEGRA124_CLK_DFLL_SOC 265
#define TEGRA124_CLK_VI_SENSOR2 266
#define TEGRA124_CLK_PLL_P_OUT5 267
#define TEGRA124_CLK_CML0 268
#define TEGRA124_CLK_CML1 269
#define TEGRA124_CLK_PLL_C4 270
#define TEGRA124_CLK_PLL_DP 271
#define TEGRA124_CLK_PLL_E_MUX 272
/* 273 */
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA124_CLK_AUDIO0_MUX 300
#define TEGRA124_CLK_AUDIO1_MUX 301
#define TEGRA124_CLK_AUDIO2_MUX 302
#define TEGRA124_CLK_AUDIO3_MUX 303
#define TEGRA124_CLK_AUDIO4_MUX 304
#define TEGRA124_CLK_SPDIF_MUX 305
#define TEGRA124_CLK_CLK_OUT_1_MUX 306
#define TEGRA124_CLK_CLK_OUT_2_MUX 307
#define TEGRA124_CLK_CLK_OUT_3_MUX 308
#define TEGRA124_CLK_DSIA_MUX 309
#define TEGRA124_CLK_DSIB_MUX 310
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_PLL_M_UD 311
#define TEGRA124_CLK_CLK_MAX 312
#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
arch/microblaze/dts/include/dt-bindings/clock/tegra20-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra20-car.
*
* The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 95 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 96 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
#define TEGRA20_CLK_CPU 0
/* 1 */
/* 2 */
#define TEGRA20_CLK_AC97 3
#define TEGRA20_CLK_RTC 4
#define TEGRA20_CLK_TIMER 5
#define TEGRA20_CLK_UARTA 6
/* 7 (register bit affects uart2 and vfir) */
#define TEGRA20_CLK_GPIO 8
#define TEGRA20_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA20_CLK_I2S1 11
#define TEGRA20_CLK_I2C1 12
#define TEGRA20_CLK_NDFLASH 13
#define TEGRA20_CLK_SDMMC1 14
#define TEGRA20_CLK_SDMMC4 15
#define TEGRA20_CLK_TWC 16
#define TEGRA20_CLK_PWM 17
#define TEGRA20_CLK_I2S2 18
#define TEGRA20_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA20_CLK_GR2D 21
#define TEGRA20_CLK_USBD 22
#define TEGRA20_CLK_ISP 23
#define TEGRA20_CLK_GR3D 24
#define TEGRA20_CLK_IDE 25
#define TEGRA20_CLK_DISP2 26
#define TEGRA20_CLK_DISP1 27
#define TEGRA20_CLK_HOST1X 28
#define TEGRA20_CLK_VCP 29
/* 30 */
#define TEGRA20_CLK_CACHE2 31
#define TEGRA20_CLK_MEM 32
#define TEGRA20_CLK_AHBDMA 33
#define TEGRA20_CLK_APBDMA 34
/* 35 */
#define TEGRA20_CLK_KBC 36
#define TEGRA20_CLK_STAT_MON 37
#define TEGRA20_CLK_PMC 38
#define TEGRA20_CLK_FUSE 39
#define TEGRA20_CLK_KFUSE 40
#define TEGRA20_CLK_SBC1 41
#define TEGRA20_CLK_NOR 42
#define TEGRA20_CLK_SPI 43
#define TEGRA20_CLK_SBC2 44
#define TEGRA20_CLK_XIO 45
#define TEGRA20_CLK_SBC3 46
#define TEGRA20_CLK_DVC 47
#define TEGRA20_CLK_DSI 48
/* 49 (register bit affects tvo and cve) */
#define TEGRA20_CLK_MIPI 50
#define TEGRA20_CLK_HDMI 51
#define TEGRA20_CLK_CSI 52
#define TEGRA20_CLK_TVDAC 53
#define TEGRA20_CLK_I2C2 54
#define TEGRA20_CLK_UARTC 55
/* 56 */
#define TEGRA20_CLK_EMC 57
#define TEGRA20_CLK_USB2 58
#define TEGRA20_CLK_USB3 59
#define TEGRA20_CLK_MPE 60
#define TEGRA20_CLK_VDE 61
#define TEGRA20_CLK_BSEA 62
#define TEGRA20_CLK_BSEV 63
#define TEGRA20_CLK_SPEEDO 64
#define TEGRA20_CLK_UARTD 65
#define TEGRA20_CLK_UARTE 66
#define TEGRA20_CLK_I2C3 67
#define TEGRA20_CLK_SBC4 68
#define TEGRA20_CLK_SDMMC3 69
#define TEGRA20_CLK_PEX 70
#define TEGRA20_CLK_OWR 71
#define TEGRA20_CLK_AFI 72
#define TEGRA20_CLK_CSITE 73
/* 74 */
#define TEGRA20_CLK_AVPUCQ 75
#define TEGRA20_CLK_LA 76
/* 77 */
/* 78 */
/* 79 */
/* 80 */
/* 81 */
/* 82 */
/* 83 */
#define TEGRA20_CLK_IRAMA 84
#define TEGRA20_CLK_IRAMB 85
#define TEGRA20_CLK_IRAMC 86
#define TEGRA20_CLK_IRAMD 87
#define TEGRA20_CLK_CRAM2 88
#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
#define TEGRA20_CLK_CLK_D 90
/* 91 */
#define TEGRA20_CLK_CSUS 92
#define TEGRA20_CLK_CDEV2 93
#define TEGRA20_CLK_CDEV1 94
/* 95 */
#define TEGRA20_CLK_UARTB 96
#define TEGRA20_CLK_VFIR 97
#define TEGRA20_CLK_SPDIF_IN 98
#define TEGRA20_CLK_SPDIF_OUT 99
#define TEGRA20_CLK_VI 100
#define TEGRA20_CLK_VI_SENSOR 101
#define TEGRA20_CLK_TVO 102
#define TEGRA20_CLK_CVE 103
#define TEGRA20_CLK_OSC 104
#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
#define TEGRA20_CLK_CLK_M 106
#define TEGRA20_CLK_SCLK 107
#define TEGRA20_CLK_CCLK 108
#define TEGRA20_CLK_HCLK 109
#define TEGRA20_CLK_PCLK 110
#define TEGRA20_CLK_BLINK 111
#define TEGRA20_CLK_PLL_A 112
#define TEGRA20_CLK_PLL_A_OUT0 113
#define TEGRA20_CLK_PLL_C 114
#define TEGRA20_CLK_PLL_C_OUT1 115
#define TEGRA20_CLK_PLL_D 116
#define TEGRA20_CLK_PLL_D_OUT0 117
#define TEGRA20_CLK_PLL_E 118
#define TEGRA20_CLK_PLL_M 119
#define TEGRA20_CLK_PLL_M_OUT1 120
#define TEGRA20_CLK_PLL_P 121
#define TEGRA20_CLK_PLL_P_OUT1 122
#define TEGRA20_CLK_PLL_P_OUT2 123
#define TEGRA20_CLK_PLL_P_OUT3 124
#define TEGRA20_CLK_PLL_P_OUT4 125
#define TEGRA20_CLK_PLL_S 126
#define TEGRA20_CLK_PLL_U 127
#define TEGRA20_CLK_PLL_X 128
#define TEGRA20_CLK_COP 129 /* a/k/a avp */
#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
#define TEGRA20_CLK_PLL_REF 131
#define TEGRA20_CLK_TWD 132
#define TEGRA20_CLK_CLK_MAX 133
#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
arch/microblaze/dts/include/dt-bindings/clock/tegra30-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra30-car.
*
* The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 160 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
#define TEGRA30_CLK_CPU 0
/* 1 */
/* 2 */
/* 3 */
#define TEGRA30_CLK_RTC 4
#define TEGRA30_CLK_TIMER 5
#define TEGRA30_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
#define TEGRA30_CLK_GPIO 8
#define TEGRA30_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA30_CLK_I2S1 11
#define TEGRA30_CLK_I2C1 12
#define TEGRA30_CLK_NDFLASH 13
#define TEGRA30_CLK_SDMMC1 14
#define TEGRA30_CLK_SDMMC4 15
/* 16 */
#define TEGRA30_CLK_PWM 17
#define TEGRA30_CLK_I2S2 18
#define TEGRA30_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA30_CLK_GR2D 21
#define TEGRA30_CLK_USBD 22
#define TEGRA30_CLK_ISP 23
#define TEGRA30_CLK_GR3D 24
/* 25 */
#define TEGRA30_CLK_DISP2 26
#define TEGRA30_CLK_DISP1 27
#define TEGRA30_CLK_HOST1X 28
#define TEGRA30_CLK_VCP 29
#define TEGRA30_CLK_I2S0 30
#define TEGRA30_CLK_COP_CACHE 31
#define TEGRA30_CLK_MC 32
#define TEGRA30_CLK_AHBDMA 33
#define TEGRA30_CLK_APBDMA 34
/* 35 */
#define TEGRA30_CLK_KBC 36
#define TEGRA30_CLK_STATMON 37
#define TEGRA30_CLK_PMC 38
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA30_CLK_KFUSE 40
#define TEGRA30_CLK_SBC1 41
#define TEGRA30_CLK_NOR 42
/* 43 */
#define TEGRA30_CLK_SBC2 44
/* 45 */
#define TEGRA30_CLK_SBC3 46
#define TEGRA30_CLK_I2C5 47
#define TEGRA30_CLK_DSIA 48
/* 49 (register bit affects cve and tvo) */
#define TEGRA30_CLK_MIPI 50
#define TEGRA30_CLK_HDMI 51
#define TEGRA30_CLK_CSI 52
#define TEGRA30_CLK_TVDAC 53
#define TEGRA30_CLK_I2C2 54
#define TEGRA30_CLK_UARTC 55
/* 56 */
#define TEGRA30_CLK_EMC 57
#define TEGRA30_CLK_USB2 58
#define TEGRA30_CLK_USB3 59
#define TEGRA30_CLK_MPE 60
#define TEGRA30_CLK_VDE 61
#define TEGRA30_CLK_BSEA 62
#define TEGRA30_CLK_BSEV 63
#define TEGRA30_CLK_SPEEDO 64
#define TEGRA30_CLK_UARTD 65
#define TEGRA30_CLK_UARTE 66
#define TEGRA30_CLK_I2C3 67
#define TEGRA30_CLK_SBC4 68
#define TEGRA30_CLK_SDMMC3 69
#define TEGRA30_CLK_PCIE 70
#define TEGRA30_CLK_OWR 71
#define TEGRA30_CLK_AFI 72
#define TEGRA30_CLK_CSITE 73
/* 74 */
#define TEGRA30_CLK_AVPUCQ 75
#define TEGRA30_CLK_LA 76
/* 77 */
/* 78 */
#define TEGRA30_CLK_DTV 79
#define TEGRA30_CLK_NDSPEED 80
#define TEGRA30_CLK_I2CSLOW 81
#define TEGRA30_CLK_DSIB 82
/* 83 */
#define TEGRA30_CLK_IRAMA 84
#define TEGRA30_CLK_IRAMB 85
#define TEGRA30_CLK_IRAMC 86
#define TEGRA30_CLK_IRAMD 87
#define TEGRA30_CLK_CRAM2 88
/* 89 */
#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
/* 91 */
#define TEGRA30_CLK_CSUS 92
#define TEGRA30_CLK_CDEV2 93
#define TEGRA30_CLK_CDEV1 94
/* 95 */
#define TEGRA30_CLK_CPU_G 96
#define TEGRA30_CLK_CPU_LP 97
#define TEGRA30_CLK_GR3D2 98
#define TEGRA30_CLK_MSELECT 99
#define TEGRA30_CLK_TSENSOR 100
#define TEGRA30_CLK_I2S3 101
#define TEGRA30_CLK_I2S4 102
#define TEGRA30_CLK_I2C4 103
#define TEGRA30_CLK_SBC5 104
#define TEGRA30_CLK_SBC6 105
#define TEGRA30_CLK_D_AUDIO 106
#define TEGRA30_CLK_APBIF 107
#define TEGRA30_CLK_DAM0 108
#define TEGRA30_CLK_DAM1 109
#define TEGRA30_CLK_DAM2 110
#define TEGRA30_CLK_HDA2CODEC_2X 111
#define TEGRA30_CLK_ATOMICS 112
#define TEGRA30_CLK_AUDIO0_2X 113
#define TEGRA30_CLK_AUDIO1_2X 114
#define TEGRA30_CLK_AUDIO2_2X 115
#define TEGRA30_CLK_AUDIO3_2X 116
#define TEGRA30_CLK_AUDIO4_2X 117
#define TEGRA30_CLK_SPDIF_2X 118
#define TEGRA30_CLK_ACTMON 119
#define TEGRA30_CLK_EXTERN1 120
#define TEGRA30_CLK_EXTERN2 121
#define TEGRA30_CLK_EXTERN3 122
#define TEGRA30_CLK_SATA_OOB 123
#define TEGRA30_CLK_SATA 124
#define TEGRA30_CLK_HDA 125
/* 126 */
#define TEGRA30_CLK_SE 127
#define TEGRA30_CLK_HDA2HDMI 128
#define TEGRA30_CLK_SATA_COLD 129
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 */
/* 144 */
/* 145 */
/* 146 */
/* 147 */
/* 148 */
/* 149 */
/* 150 */
/* 151 */
/* 152 */
/* 153 */
/* 154 */
/* 155 */
/* 156 */
/* 157 */
/* 158 */
/* 159 */
#define TEGRA30_CLK_UARTB 160
#define TEGRA30_CLK_VFIR 161
#define TEGRA30_CLK_SPDIF_IN 162
#define TEGRA30_CLK_SPDIF_OUT 163
#define TEGRA30_CLK_VI 164
#define TEGRA30_CLK_VI_SENSOR 165
#define TEGRA30_CLK_FUSE 166
#define TEGRA30_CLK_FUSE_BURN 167
#define TEGRA30_CLK_CVE 168
#define TEGRA30_CLK_TVO 169
#define TEGRA30_CLK_CLK_32K 170
#define TEGRA30_CLK_CLK_M 171
#define TEGRA30_CLK_CLK_M_DIV2 172
#define TEGRA30_CLK_CLK_M_DIV4 173
#define TEGRA30_CLK_PLL_REF 174
#define TEGRA30_CLK_PLL_C 175
#define TEGRA30_CLK_PLL_C_OUT1 176
#define TEGRA30_CLK_PLL_M 177
#define TEGRA30_CLK_PLL_M_OUT1 178
#define TEGRA30_CLK_PLL_P 179
#define TEGRA30_CLK_PLL_P_OUT1 180
#define TEGRA30_CLK_PLL_P_OUT2 181
#define TEGRA30_CLK_PLL_P_OUT3 182
#define TEGRA30_CLK_PLL_P_OUT4 183
#define TEGRA30_CLK_PLL_A 184
#define TEGRA30_CLK_PLL_A_OUT0 185
#define TEGRA30_CLK_PLL_D 186
#define TEGRA30_CLK_PLL_D_OUT0 187
#define TEGRA30_CLK_PLL_D2 188
#define TEGRA30_CLK_PLL_D2_OUT0 189
#define TEGRA30_CLK_PLL_U 190
#define TEGRA30_CLK_PLL_X 191
#define TEGRA30_CLK_PLL_X_OUT0 192
#define TEGRA30_CLK_PLL_E 193
#define TEGRA30_CLK_SPDIF_IN_SYNC 194
#define TEGRA30_CLK_I2S0_SYNC 195
#define TEGRA30_CLK_I2S1_SYNC 196
#define TEGRA30_CLK_I2S2_SYNC 197
#define TEGRA30_CLK_I2S3_SYNC 198
#define TEGRA30_CLK_I2S4_SYNC 199
#define TEGRA30_CLK_VIMCLK_SYNC 200
#define TEGRA30_CLK_AUDIO0 201
#define TEGRA30_CLK_AUDIO1 202
#define TEGRA30_CLK_AUDIO2 203
#define TEGRA30_CLK_AUDIO3 204
#define TEGRA30_CLK_AUDIO4 205
#define TEGRA30_CLK_SPDIF 206
#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
#define TEGRA30_CLK_SCLK 210
#define TEGRA30_CLK_BLINK 211
#define TEGRA30_CLK_CCLK_G 212
#define TEGRA30_CLK_CCLK_LP 213
#define TEGRA30_CLK_TWD 214
#define TEGRA30_CLK_CML0 215
#define TEGRA30_CLK_CML1 216
#define TEGRA30_CLK_HCLK 217
#define TEGRA30_CLK_PCLK 218
/* 219 */
/* 220 */
/* 221 */
/* 222 */
/* 223 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA30_CLK_CLK_OUT_1_MUX 300
#define TEGRA30_CLK_CLK_OUT_2_MUX 301
#define TEGRA30_CLK_CLK_OUT_3_MUX 302
#define TEGRA30_CLK_AUDIO0_MUX 303
#define TEGRA30_CLK_AUDIO1_MUX 304
#define TEGRA30_CLK_AUDIO2_MUX 305
#define TEGRA30_CLK_AUDIO3_MUX 306
#define TEGRA30_CLK_AUDIO4_MUX 307
#define TEGRA30_CLK_SPDIF_MUX 308
#define TEGRA30_CLK_CLK_MAX 309
#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
arch/microblaze/dts/include/dt-bindings/gpio/gpio.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for most GPIO bindings.
*
* Most GPIO bindings include a flags cell as part of the GPIO specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_GPIO_GPIO_H
#define _DT_BINDINGS_GPIO_GPIO_H
#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1
#endif
arch/microblaze/dts/include/dt-bindings/gpio/tegra-gpio.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra*-gpio.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#include <dt-bindings/gpio/gpio.h>
#define TEGRA_GPIO_BANK_ID_A 0
#define TEGRA_GPIO_BANK_ID_B 1
#define TEGRA_GPIO_BANK_ID_C 2
#define TEGRA_GPIO_BANK_ID_D 3
#define TEGRA_GPIO_BANK_ID_E 4
#define TEGRA_GPIO_BANK_ID_F 5
#define TEGRA_GPIO_BANK_ID_G 6
#define TEGRA_GPIO_BANK_ID_H 7
#define TEGRA_GPIO_BANK_ID_I 8
#define TEGRA_GPIO_BANK_ID_J 9
#define TEGRA_GPIO_BANK_ID_K 10
#define TEGRA_GPIO_BANK_ID_L 11
#define TEGRA_GPIO_BANK_ID_M 12
#define TEGRA_GPIO_BANK_ID_N 13
#define TEGRA_GPIO_BANK_ID_O 14
#define TEGRA_GPIO_BANK_ID_P 15
#define TEGRA_GPIO_BANK_ID_Q 16
#define TEGRA_GPIO_BANK_ID_R 17
#define TEGRA_GPIO_BANK_ID_S 18
#define TEGRA_GPIO_BANK_ID_T 19
#define TEGRA_GPIO_BANK_ID_U 20
#define TEGRA_GPIO_BANK_ID_V 21
#define TEGRA_GPIO_BANK_ID_W 22
#define TEGRA_GPIO_BANK_ID_X 23
#define TEGRA_GPIO_BANK_ID_Y 24
#define TEGRA_GPIO_BANK_ID_Z 25
#define TEGRA_GPIO_BANK_ID_AA 26
#define TEGRA_GPIO_BANK_ID_BB 27
#define TEGRA_GPIO_BANK_ID_CC 28
#define TEGRA_GPIO_BANK_ID_DD 29
#define TEGRA_GPIO_BANK_ID_EE 30
#define TEGRA_GPIO_BANK_ID_FF 31
#define TEGRA_GPIO(bank, offset) \
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
#endif
arch/microblaze/dts/include/dt-bindings/interrupt-controller/arm-gic.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for the ARM GIC.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
#include <dt-bindings/interrupt-controller/irq.h>
/* interrupt specific cell 0 */
#define GIC_SPI 0
#define GIC_PPI 1
/*
* Interrupt specifier cell 2.
* The flaggs in irq.h are valid, plus those below.
*/
#define GIC_CPU_MASK_RAW(x) ((x) << 8)
#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
#endif
arch/microblaze/dts/include/dt-bindings/interrupt-controller/irq.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for most IRQ bindings.
*
* Most IRQ bindings include a flags cell as part of the IRQ specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define IRQ_TYPE_NONE 0
#define IRQ_TYPE_EDGE_RISING 1
#define IRQ_TYPE_EDGE_FALLING 2
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
#endif
arch/sandbox/dts/include/dt-bindings 0 → 120000
View file @ d1bdfe37
../../../../include/dt-bindings
\ No newline at end of file
arch/sandbox/dts/include/dt-bindings/clock/tegra114-car.h deleted 100755 → 0
View file @ 23e1ad66
/*
* This header provides constants for binding nvidia,tegra114-car.
*
* The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 160 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
/* 0 */
/* 1 */
/* 2 */
/* 3 */
#define TEGRA114_CLK_RTC 4
#define TEGRA114_CLK_TIMER 5
#define TEGRA114_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA114_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA114_CLK_I2S1 11
#define TEGRA114_CLK_I2C1 12
#define TEGRA114_CLK_NDFLASH 13
#define TEGRA114_CLK_SDMMC1 14
#define TEGRA114_CLK_SDMMC4 15
/* 16 */
#define TEGRA114_CLK_PWM 17
#define TEGRA114_CLK_I2S2 18
#define TEGRA114_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA114_CLK_GR2D 21
#define TEGRA114_CLK_USBD 22
#define TEGRA114_CLK_ISP 23
#define TEGRA114_CLK_GR3D 24
/* 25 */
#define TEGRA114_CLK_DISP2 26
#define TEGRA114_CLK_DISP1 27
#define TEGRA114_CLK_HOST1X 28
#define TEGRA114_CLK_VCP 29
#define TEGRA114_CLK_I2S0 30
/* 31 */
/* 32 */
/* 33 */
#define TEGRA114_CLK_APBDMA 34
/* 35 */
#define TEGRA114_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA114_CLK_KFUSE 40
#define TEGRA114_CLK_SBC1 41
#define TEGRA114_CLK_NOR 42
/* 43 */
#define TEGRA114_CLK_SBC2 44
/* 45 */
#define TEGRA114_CLK_SBC3 46
#define TEGRA114_CLK_I2C5 47
#define TEGRA114_CLK_DSIA 48
/* 49 */
#define TEGRA114_CLK_MIPI 50
#define TEGRA114_CLK_HDMI 51
#define TEGRA114_CLK_CSI 52
/* 53 */
#define TEGRA114_CLK_I2C2 54
#define TEGRA114_CLK_UARTC 55
#define TEGRA114_CLK_MIPI_CAL 56
#define TEGRA114_CLK_EMC 57
#define TEGRA114_CLK_USB2 58
#define TEGRA114_CLK_USB3 59
/* 60 */
#define TEGRA114_CLK_VDE 61
#define TEGRA114_CLK_BSEA 62
#define TEGRA114_CLK_BSEV 63
/* 64 */
#define TEGRA114_CLK_UARTD 65
/* 66 */
#define TEGRA114_CLK_I2C3 67
#define TEGRA114_CLK_SBC4 68
#define TEGRA114_CLK_SDMMC3 69
/* 70 */
#define TEGRA114_CLK_OWR 71
/* 72 */
#define TEGRA114_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA114_CLK_LA 76
#define TEGRA114_CLK_TRACE 77
#define TEGRA114_CLK_SOC_THERM 78
#define TEGRA114_CLK_DTV 79
#define TEGRA114_CLK_NDSPEED 80
#define TEGRA114_CLK_I2CSLOW 81
#define TEGRA114_CLK_DSIB 82
#define TEGRA114_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA114_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA114_CLK_MSENC 91
#define TEGRA114_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA114_CLK_MSELECT 99
#define TEGRA114_CLK_TSENSOR 100
#define TEGRA114_CLK_I2S3 101
#define TEGRA114_CLK_I2S4 102
#define TEGRA114_CLK_I2C4 103
#define TEGRA114_CLK_SBC5 104
#define TEGRA114_CLK_SBC6 105
#define TEGRA114_CLK_D_AUDIO 106
#define TEGRA114_CLK_APBIF 107
#define TEGRA114_CLK_DAM0 108
#define TEGRA114_CLK_DAM1 109
#define TEGRA114_CLK_DAM2 110
#define TEGRA114_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA114_CLK_AUDIO0_2X 113
#define TEGRA114_CLK_AUDIO1_2X 114
#define TEGRA114_CLK_AUDIO2_2X 115
#define TEGRA114_CLK_AUDIO3_2X 116
#define TEGRA114_CLK_AUDIO4_2X 117
#define TEGRA114_CLK_SPDIF_2X 118
#define TEGRA114_CLK_ACTMON 119
#define TEGRA114_CLK_EXTERN1 120
#define TEGRA114_CLK_EXTERN2 121
#define TEGRA114_CLK_EXTERN3 122
/* 123 */
/* 124 */
#define TEGRA114_CLK_HDA 125
/* 126 */
#define TEGRA114_CLK_SE 127
#define TEGRA114_CLK_HDA2HDMI 128
/* 129 */
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA114_CLK_CILAB 144
#define TEGRA114_CLK_CILCD 145
#define TEGRA114_CLK_CILE 146
#define TEGRA114_CLK_DSIALP 147
#define TEGRA114_CLK_DSIBLP 148
/* 149 */
#define TEGRA114_CLK_DDS 150
/* 151 */
#define TEGRA114_CLK_DP2 152
#define TEGRA114_CLK_AMX 153
#define TEGRA114_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA114_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
/* 166 */
/* 167 */
/* 168 */
/* 169 */
/* 170 */
/* 171 */
/* 172 */
/* 173 */
/* 174 */
/* 175 */
/* 176 */
/* 177 */
/* 178 */
/* 179 */
/* 180 */
/* 181 */
/* 182 */
/* 183 */
/* 184 */
/* 185 */
/* 186 */
/* 187 */
/* 188 */
/* 189 */
/* 190 */
/* 191 */
#define TEGRA114_CLK_UARTB 192
#define TEGRA114_CLK_VFIR 193
#define TEGRA114_CLK_SPDIF_IN 194
#define TEGRA114_CLK_SPDIF_OUT 195
#define TEGRA114_CLK_VI 196
#define TEGRA114_CLK_VI_SENSOR 197
#define TEGRA114_CLK_FUSE 198
#define TEGRA114_CLK_FUSE_BURN 199
#define TEGRA114_CLK_CLK_32K 200
#define TEGRA114_CLK_CLK_M 201
#define TEGRA114_CLK_CLK_M_DIV2 202
#define TEGRA114_CLK_CLK_M_DIV4 203
#define TEGRA114_CLK_PLL_REF 204
#define TEGRA114_CLK_PLL_C 205
#define TEGRA114_CLK_PLL_C_OUT1 206
#define TEGRA114_CLK_PLL_C2 207
#define TEGRA114_CLK_PLL_C3 208
#define TEGRA114_CLK_PLL_M 209
#define TEGRA114_CLK_PLL_M_OUT1 210
#define TEGRA114_CLK_PLL_P 211
#define TEGRA114_CLK_PLL_P_OUT1 212
#define TEGRA114_CLK_PLL_P_OUT2 213
#define TEGRA114_CLK_PLL_P_OUT3 214
#define TEGRA114_CLK_PLL_P_OUT4 215
#define TEGRA114_CLK_PLL_A 216
#define TEGRA114_CLK_PLL_A_OUT0 217
#define TEGRA114_CLK_PLL_D 218
#define TEGRA114_CLK_PLL_D_OUT0 219
#define TEGRA114_CLK_PLL_D2 220
#define TEGRA114_CLK_PLL_D2_OUT0 221
#define TEGRA114_CLK_PLL_U 222
#define TEGRA114_CLK_PLL_U_480M 223
#define TEGRA114_CLK_PLL_U_60M 224
#define TEGRA114_CLK_PLL_U_48M 225
#define TEGRA114_CLK_PLL_U_12M 226
#define TEGRA114_CLK_PLL_X 227
#define TEGRA114_CLK_PLL_X_OUT0 228
#define TEGRA114_CLK_PLL_RE_VCO 229
#define TEGRA114_CLK_PLL_RE_OUT 230
#define TEGRA114_CLK_PLL_E_OUT0 231
#define TEGRA114_CLK_SPDIF_IN_SYNC 232
#define TEGRA114_CLK_I2S0_SYNC 233
#define TEGRA114_CLK_I2S1_SYNC 234
#define TEGRA114_CLK_I2S2_SYNC 235
#define TEGRA114_CLK_I2S3_SYNC 236
#define TEGRA114_CLK_I2S4_SYNC 237
#define TEGRA114_CLK_VIMCLK_SYNC 238
#define TEGRA114_CLK_AUDIO0 239
#define TEGRA114_CLK_AUDIO1 240
#define TEGRA114_CLK_AUDIO2 241
#define TEGRA114_CLK_AUDIO3 242
#define TEGRA114_CLK_AUDIO4 243
#define TEGRA114_CLK_SPDIF 244
#define TEGRA114_CLK_CLK_OUT_1 245
#define TEGRA114_CLK_CLK_OUT_2 246
#define TEGRA114_CLK_CLK_OUT_3 247
#define TEGRA114_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA114_CLK_XUSB_HOST_SRC 252
#define TEGRA114_CLK_XUSB_FALCON_SRC 253
#define TEGRA114_CLK_XUSB_FS_SRC 254
#define TEGRA114_CLK_XUSB_SS_SRC 255
#define TEGRA114_CLK_XUSB_DEV_SRC 256
#define TEGRA114_CLK_XUSB_DEV 257
#define TEGRA114_CLK_XUSB_HS_SRC 258
#define TEGRA114_CLK_SCLK 259
#define TEGRA114_CLK_HCLK 260
#define TEGRA114_CLK_PCLK 261
#define TEGRA114_CLK_CCLK_G 262
#define TEGRA114_CLK_CCLK_LP 263
#define TEGRA114_CLK_DFLL_REF 264
#define TEGRA114_CLK_DFLL_SOC 265
/* 266 */
/* 267 */
/* 268 */
/* 269 */
/* 270 */
/* 271 */
/* 272 */
/* 273 */
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA114_CLK_AUDIO0_MUX 300
#define TEGRA114_CLK_AUDIO1_MUX 301
#define TEGRA114_CLK_AUDIO2_MUX 302
#define TEGRA114_CLK_AUDIO3_MUX 303
#define TEGRA114_CLK_AUDIO4_MUX 304
#define TEGRA114_CLK_SPDIF_MUX 305
#define TEGRA114_CLK_CLK_OUT_1_MUX 306
#define TEGRA114_CLK_CLK_OUT_2_MUX 307
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_CLK_MAX 311
#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
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