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Commit c737bc23 authored by Adam Langley's avatar Adam Langley Committed by Android Git Automerger
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am 3781a606: am 1e4884f6: external/boringssl: sync with upstream. 

* commit '3781a606':
  external/boringssl: sync with upstream.
parents 0267d647 3781a606
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BORINGSSL_REVISION
View file @ c737bc23
af0e32cb84f0c9cc65b9233a3414d2562642b342
d98dc1311e20193ac188e359e91aeaaf5cc3a7e2
UPDATING 0 → 100644
View file @ c737bc23
rm -Rf src
git clone https://boringssl.googlesource.com/boringssl src
cd src
git show -s --pretty=%H > ../BORINGSSL_REVISION
cd ..
rm -Rf src/.git
rm -Rf linux-aarch64/ linux-arm/ linux-x86/ linux-x86_64/ mac-x86/ mac-x86_64/ win-x86_64/ win-x86/
python src/util/generate_build_files.py android
crypto-sources.mk
View file @ c737bc23
LOCAL_ADDITIONAL_DEPENDENCIES += $(LOCAL_PATH)/sources.mk
include $(LOCAL_PATH)/sources.mk
LOCAL_CFLAGS += -I$(LOCAL_PATH)/src/include -I$(LOCAL_PATH)/src/crypto -Wno-unused-parameter
LOCAL_CFLAGS += -I$(LOCAL_PATH)/src/include -I$(LOCAL_PATH)/src/crypto -Wno-unused-parameter -DBORINGSSL_ANDROID_SYSTEM
LOCAL_ASFLAGS += -I$(LOCAL_PATH)/src/include -I$(LOCAL_PATH)/src/crypto -Wno-unused-parameter
# Do not add in the architecture-specific files if we don't want to build assembly
ifeq ($(LOCAL_IS_HOST_MODULE),true)
LOCAL_SRC_FILES_linux_x86 := $(linux_x86_sources)
......
err_data.c
View file @ c737bc23
This diff is collapsed.
linux-aarch64/crypto/aes/aesv8-armx.S → linux-aarch64/crypto/aes/aesv8-armx64.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__aarch64__)
#include <openssl/arm_arch.h>
#if __ARM_MAX_ARCH__>=7
.text
......@@ -747,3 +748,4 @@ aes_v8_ctr32_encrypt_blocks:
ret
.size aes_v8_ctr32_encrypt_blocks,.-aes_v8_ctr32_encrypt_blocks
#endif
#endif
\ No newline at end of file
linux-aarch64/crypto/modes/ghashv8-armx.S → linux-aarch64/crypto/modes/ghashv8-armx64.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__aarch64__)
#include <openssl/arm_arch.h>
.text
#if !defined(__clang__)
......@@ -67,10 +68,10 @@ gcm_gmult_v8:
#endif
ext v3.16b,v17.16b,v17.16b,#8
pmull v0.1q,v20.1d,v3.1d //H.loXi.lo
pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
eor v17.16b,v17.16b,v3.16b //Karatsuba pre-processing
pmull2 v2.1q,v20.2d,v3.2d //H.hiXi.hi
pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)(Xi.lo+Xi.hi)
pmull2 v2.1q,v20.2d,v3.2d //H.hi·Xi.hi
pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
eor v18.16b,v0.16b,v2.16b
......@@ -134,7 +135,7 @@ gcm_ghash_v8:
#endif
ext v7.16b,v17.16b,v17.16b,#8
eor v3.16b,v3.16b,v0.16b //I[i]^=Xi
pmull v4.1q,v20.1d,v7.1d //HIi+1
pmull v4.1q,v20.1d,v7.1d //H·Ii+1
eor v17.16b,v17.16b,v7.16b //Karatsuba pre-processing
pmull2 v6.1q,v20.2d,v7.2d
b .Loop_mod2x_v8
......@@ -143,14 +144,14 @@ gcm_ghash_v8:
.Loop_mod2x_v8:
ext v18.16b,v3.16b,v3.16b,#8
subs x3,x3,#32 //is there more data?
pmull v0.1q,v22.1d,v3.1d //H^2.loXi.lo
pmull v0.1q,v22.1d,v3.1d //H^2.lo·Xi.lo
csel x12,xzr,x12,lo //is it time to zero x12?
pmull v5.1q,v21.1d,v17.1d
eor v18.16b,v18.16b,v3.16b //Karatsuba pre-processing
pmull2 v2.1q,v22.2d,v3.2d //H^2.hiXi.hi
pmull2 v2.1q,v22.2d,v3.2d //H^2.hi·Xi.hi
eor v0.16b,v0.16b,v4.16b //accumulate
pmull2 v1.1q,v21.2d,v18.2d //(H^2.lo+H^2.hi)(Xi.lo+Xi.hi)
pmull2 v1.1q,v21.2d,v18.2d //(H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
ld1 {v16.2d},[x2],x12 //load [rotated] I[i+2]
eor v2.16b,v2.16b,v6.16b
......@@ -175,7 +176,7 @@ gcm_ghash_v8:
ext v7.16b,v17.16b,v17.16b,#8
ext v3.16b,v16.16b,v16.16b,#8
eor v0.16b,v1.16b,v18.16b
pmull v4.1q,v20.1d,v7.1d //HIi+1
pmull v4.1q,v20.1d,v7.1d //H·Ii+1
eor v3.16b,v3.16b,v2.16b //accumulate v3.16b early
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
......@@ -196,10 +197,10 @@ gcm_ghash_v8:
eor v3.16b,v3.16b,v0.16b //inp^=Xi
eor v17.16b,v16.16b,v18.16b //v17.16b is rotated inp^Xi
pmull v0.1q,v20.1d,v3.1d //H.loXi.lo
pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
eor v17.16b,v17.16b,v3.16b //Karatsuba pre-processing
pmull2 v2.1q,v20.2d,v3.2d //H.hiXi.hi
pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)(Xi.lo+Xi.hi)
pmull2 v2.1q,v20.2d,v3.2d //H.hi·Xi.hi
pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
eor v18.16b,v0.16b,v2.16b
......@@ -228,3 +229,4 @@ gcm_ghash_v8:
.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.align 2
.align 2
#endif
\ No newline at end of file
linux-aarch64/crypto/sha/sha1-armv8.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__aarch64__)
#include <openssl/arm_arch.h>
.text
......@@ -1211,3 +1212,4 @@ sha1_block_armv8:
.align 2
.align 2
.comm OPENSSL_armcap_P,4,4
#endif
\ No newline at end of file
linux-aarch64/crypto/sha/sha256-armv8.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__aarch64__)
#include <openssl/arm_arch.h>
.text
......@@ -1141,3 +1142,4 @@ sha256_block_armv8:
ret
.size sha256_block_armv8,.-sha256_block_armv8
.comm OPENSSL_armcap_P,4,4
#endif
\ No newline at end of file
linux-aarch64/crypto/sha/sha512-armv8.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__aarch64__)
#include <openssl/arm_arch.h>
.text
......@@ -1021,3 +1022,4 @@ sha512_block_data_order:
.align 2
.align 2
.comm OPENSSL_armcap_P,4,4
#endif
\ No newline at end of file
linux-arm/crypto/aes/aes-armv4.S
View file @ c737bc23
#if defined(__arm__)
@ ====================================================================
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
......@@ -33,7 +34,7 @@
#if defined(__arm__)
#ifndef __KERNEL__
# include "arm_arch.h"
# include <openssl/arm_arch.h>
#else
# define __ARM_ARCH__ __LINUX_ARM_ARCH__
#endif
......@@ -1196,3 +1197,4 @@ _armv4_AES_decrypt:
.align 2
#endif
#endif
\ No newline at end of file
linux-arm/crypto/aes/aesv8-armx.S → linux-arm/crypto/aes/aesv8-armx32.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__arm__)
#include <openssl/arm_arch.h>
#if __ARM_MAX_ARCH__>=7
.text
......@@ -752,3 +753,4 @@ aes_v8_ctr32_encrypt_blocks:
ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,pc}
.size aes_v8_ctr32_encrypt_blocks,.-aes_v8_ctr32_encrypt_blocks
#endif
#endif
\ No newline at end of file
linux-arm/crypto/aes/bsaes-armv7.S
View file @ c737bc23
#if defined(__arm__)
@ ====================================================================
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
......@@ -48,7 +49,7 @@
#if defined(__arm__)
#ifndef __KERNEL__
# include "arm_arch.h"
# include <openssl/arm_arch.h>
# define VFP_ABI_PUSH vstmdb sp!,{d8-d15}
# define VFP_ABI_POP vldmia sp!,{d8-d15}
......@@ -2575,3 +2576,4 @@ bsaes_xts_decrypt:
.size bsaes_xts_decrypt,.-bsaes_xts_decrypt
#endif
#endif
#endif
\ No newline at end of file
linux-arm/crypto/bn/armv4-mont.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__arm__)
#include <openssl/arm_arch.h>
.text
.code 32
......@@ -585,3 +586,4 @@ bn_mul8x_mont_neon:
.comm OPENSSL_armcap_P,4,4
.hidden OPENSSL_armcap_P
#endif
#endif
\ No newline at end of file
linux-arm/crypto/modes/ghash-armv4.S
View file @ c737bc23
#if defined(__arm__)
#include "arm_arch.h"
#if defined(__arm__)
#include <openssl/arm_arch.h>
.syntax unified
......@@ -537,3 +538,4 @@ gcm_ghash_neon:
.align 2
#endif
#endif
\ No newline at end of file
linux-arm/crypto/modes/ghashv8-armx.S → linux-arm/crypto/modes/ghashv8-armx32.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__arm__)
#include <openssl/arm_arch.h>
.text
.fpu neon
......@@ -66,10 +67,10 @@ gcm_gmult_v8:
#endif
vext.8 q3,q9,q9,#8
.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.loXi.lo
.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
veor q9,q9,q3 @ Karatsuba pre-processing
.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hiXi.hi
.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)(Xi.lo+Xi.hi)
.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hi·Xi.hi
.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
veor q10,q0,q2
......@@ -134,7 +135,7 @@ gcm_ghash_v8:
#endif
vext.8 q7,q9,q9,#8
veor q3,q3,q0 @ I[i]^=Xi
.byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ HIi+1
.byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1
veor q9,q9,q7 @ Karatsuba pre-processing
.byte 0x8f,0xce,0xa9,0xf2 @ pmull2 q6,q12,q7
b .Loop_mod2x_v8
......@@ -143,14 +144,14 @@ gcm_ghash_v8:
.Loop_mod2x_v8:
vext.8 q10,q3,q3,#8
subs r3,r3,#32 @ is there more data?
.byte 0x86,0x0e,0xac,0xf2 @ pmull q0,q14,q3 @ H^2.loXi.lo
.byte 0x86,0x0e,0xac,0xf2 @ pmull q0,q14,q3 @ H^2.lo·Xi.lo
movlo r12,#0 @ is it time to zero r12?
.byte 0xa2,0xae,0xaa,0xf2 @ pmull q5,q13,q9
veor q10,q10,q3 @ Karatsuba pre-processing
.byte 0x87,0x4e,0xad,0xf2 @ pmull2 q2,q14,q3 @ H^2.hiXi.hi
.byte 0x87,0x4e,0xad,0xf2 @ pmull2 q2,q14,q3 @ H^2.hi·Xi.hi
veor q0,q0,q4 @ accumulate
.byte 0xa5,0x2e,0xab,0xf2 @ pmull2 q1,q13,q10 @ (H^2.lo+H^2.hi)(Xi.lo+Xi.hi)
.byte 0xa5,0x2e,0xab,0xf2 @ pmull2 q1,q13,q10 @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
vld1.64 {q8},[r2],r12 @ load [rotated] I[i+2]
veor q2,q2,q6
......@@ -175,7 +176,7 @@ gcm_ghash_v8:
vext.8 q7,q9,q9,#8
vext.8 q3,q8,q8,#8
veor q0,q1,q10
.byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ HIi+1
.byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1
veor q3,q3,q2 @ accumulate q3 early
vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
......@@ -196,10 +197,10 @@ gcm_ghash_v8:
veor q3,q3,q0 @ inp^=Xi
veor q9,q8,q10 @ q9 is rotated inp^Xi
.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.loXi.lo
.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
veor q9,q9,q3 @ Karatsuba pre-processing
.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hiXi.hi
.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)(Xi.lo+Xi.hi)
.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hi·Xi.hi
.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
veor q10,q0,q2
......@@ -229,3 +230,4 @@ gcm_ghash_v8:
.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.align 2
.align 2
#endif
\ No newline at end of file
linux-arm/crypto/sha/sha1-armv4-large.S
View file @ c737bc23
#include "arm_arch.h"
#if defined(__arm__)
#include <openssl/arm_arch.h>
.text
.code 32
......@@ -1458,3 +1459,4 @@ sha1_block_data_order_armv8:
.comm OPENSSL_armcap_P,4,4
.hidden OPENSSL_armcap_P
#endif
#endif
\ No newline at end of file
linux-arm/crypto/sha/sha256-armv4.S
View file @ c737bc23
#if defined(__arm__)
@ ====================================================================
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
......@@ -37,7 +38,7 @@
@ Add ARMv8 code path performing at 2.0 cpb on Apple A7.
#ifndef __KERNEL__
# include "arm_arch.h"
# include <openssl/arm_arch.h>
#else
# define __ARM_ARCH__ __LINUX_ARM_ARCH__
# define __ARM_MAX_ARCH__ 7
......@@ -2814,3 +2815,4 @@ sha256_block_data_order_armv8:
.comm OPENSSL_armcap_P,4,4
.hidden OPENSSL_armcap_P
#endif
#endif
\ No newline at end of file
linux-arm/crypto/sha/sha512-armv4.S
View file @ c737bc23
#if defined(__arm__)
@ ====================================================================
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
......@@ -46,7 +47,7 @@
@ was reflected in below two parameters as 0 and 4. Now caller is
@ expected to maintain native byte order for whole 64-bit values.
#ifndef __KERNEL__
# include "arm_arch.h"
# include <openssl/arm_arch.h>
# define VFP_ABI_PUSH vstmdb sp!,{d8-d15}
# define VFP_ABI_POP vldmia sp!,{d8-d15}
#else
......@@ -1865,3 +1866,4 @@ sha512_block_data_order_neon:
.comm OPENSSL_armcap_P,4,4
.hidden OPENSSL_armcap_P
#endif
#endif
\ No newline at end of file
linux-x86/crypto/cpu-x86-asm.S deleted 100644 → 0
View file @ 0267d647
#if defined(__i386__)
.file "crypto/cpu-x86-asm.S"
.text
.globl OPENSSL_ia32_cpuid
.hidden OPENSSL_ia32_cpuid
.type OPENSSL_ia32_cpuid,@function
.align 16
OPENSSL_ia32_cpuid:
.L_OPENSSL_ia32_cpuid_begin:
pushl %ebp
pushl %ebx
pushl %esi
pushl %edi
xorl %edx,%edx
pushfl
popl %eax
movl %eax,%ecx
xorl $2097152,%eax
pushl %eax
popfl
pushfl
popl %eax
xorl %eax,%ecx
xorl %eax,%eax
btl $21,%ecx
jnc .L000nocpuid
movl 20(%esp),%esi
movl %eax,8(%esi)
.byte 0x0f,0xa2
movl %eax,%edi
xorl %eax,%eax
cmpl $1970169159,%ebx
setne %al
movl %eax,%ebp
cmpl $1231384169,%edx
setne %al
orl %eax,%ebp
cmpl $1818588270,%ecx
setne %al
orl %eax,%ebp
jz .L001intel
cmpl $1752462657,%ebx
setne %al
movl %eax,%esi
cmpl $1769238117,%edx
setne %al
orl %eax,%esi
cmpl $1145913699,%ecx
setne %al
orl %eax,%esi
jnz .L001intel
movl $2147483648,%eax
.byte 0x0f,0xa2
cmpl $2147483649,%eax
jb .L001intel
movl %eax,%esi
movl $2147483649,%eax
.byte 0x0f,0xa2
orl %ecx,%ebp
andl $2049,%ebp
cmpl $2147483656,%esi
jb .L001intel
movl $2147483656,%eax
.byte 0x0f,0xa2
movzbl %cl,%esi
incl %esi
movl $1,%eax
xorl %ecx,%ecx
.byte 0x0f,0xa2
btl $28,%edx
jnc .L002generic
shrl $16,%ebx
andl $255,%ebx
cmpl %esi,%ebx
ja .L002generic
andl $4026531839,%edx
jmp .L002generic
.L001intel:
cmpl $7,%edi
jb .L003cacheinfo
movl 20(%esp),%esi
movl $7,%eax
xorl %ecx,%ecx
.byte 0x0f,0xa2
movl %ebx,8(%esi)
.L003cacheinfo:
cmpl $4,%edi
movl $-1,%edi
jb .L004nocacheinfo
movl $4,%eax
movl $0,%ecx
.byte 0x0f,0xa2
movl %eax,%edi
shrl $14,%edi
andl $4095,%edi
.L004nocacheinfo:
movl $1,%eax
xorl %ecx,%ecx
.byte 0x0f,0xa2
andl $3220176895,%edx
cmpl $0,%ebp
jne .L005notintel
orl $1073741824,%edx
.L005notintel:
btl $28,%edx
jnc .L002generic
andl $4026531839,%edx
cmpl $0,%edi
je .L002generic
orl $268435456,%edx
shrl $16,%ebx
cmpb $1,%bl
ja .L002generic
andl $4026531839,%edx
.L002generic:
andl $2048,%ebp
andl $4294965247,%ecx
movl %edx,%esi
orl %ecx,%ebp
btl $27,%ecx
jnc .L006clear_avx
xorl %ecx,%ecx
.byte 15,1,208
andl $6,%eax
cmpl $6,%eax
je .L007done
cmpl $2,%eax
je .L006clear_avx
.L008clear_xmm:
andl $4261412861,%ebp
andl $4278190079,%esi
.L006clear_avx:
andl $4026525695,%ebp
movl 20(%esp),%edi
andl $4294967263,8(%edi)
.L007done:
movl %esi,%eax
movl %ebp,%edx
.L000nocpuid:
popl %edi
popl %esi
popl %ebx
popl %ebp
ret
.size OPENSSL_ia32_cpuid,.-.L_OPENSSL_ia32_cpuid_begin
.globl OPENSSL_rdtsc
.hidden OPENSSL_rdtsc
.type OPENSSL_rdtsc,@function
.align 16
OPENSSL_rdtsc:
.L_OPENSSL_rdtsc_begin:
xorl %eax,%eax
xorl %edx,%edx
call .L009PIC_me_up
.L009PIC_me_up:
popl %ecx
leal OPENSSL_ia32cap_P-.L009PIC_me_up(%ecx),%ecx
btl $4,(%ecx)
jnc .L010notsc
.byte 0x0f,0x31
.L010notsc:
ret
.size OPENSSL_rdtsc,.-.L_OPENSSL_rdtsc_begin
.globl OPENSSL_instrument_halt
.hidden OPENSSL_instrument_halt
.type OPENSSL_instrument_halt,@function
.align 16
OPENSSL_instrument_halt:
.L_OPENSSL_instrument_halt_begin:
call .L011PIC_me_up
.L011PIC_me_up:
popl %ecx
leal OPENSSL_ia32cap_P-.L011PIC_me_up(%ecx),%ecx
btl $4,(%ecx)
jnc .L012nohalt
.long 2421723150
andl $3,%eax
jnz .L012nohalt
pushfl
popl %eax
btl $9,%eax
jnc .L012nohalt
.byte 0x0f,0x31
pushl %edx
pushl %eax
hlt
.byte 0x0f,0x31
subl (%esp),%eax
sbbl 4(%esp),%edx
addl $8,%esp
ret
.L012nohalt:
xorl %eax,%eax
xorl %edx,%edx
ret
.size OPENSSL_instrument_halt,.-.L_OPENSSL_instrument_halt_begin
.globl OPENSSL_far_spin
.hidden OPENSSL_far_spin
.type OPENSSL_far_spin,@function
.align 16
OPENSSL_far_spin:
.L_OPENSSL_far_spin_begin:
pushfl
popl %eax
btl $9,%eax
jnc .L013nospin
movl 4(%esp),%eax
movl 8(%esp),%ecx
.long 2430111262
xorl %eax,%eax
movl (%ecx),%edx
jmp .L014spin
.align 16
.L014spin:
incl %eax
cmpl (%ecx),%edx
je .L014spin
.long 529567888
ret
.L013nospin:
xorl %eax,%eax
xorl %edx,%edx
ret
.size OPENSSL_far_spin,.-.L_OPENSSL_far_spin_begin
.globl OPENSSL_wipe_cpu
.hidden OPENSSL_wipe_cpu
.type OPENSSL_wipe_cpu,@function
.align 16
OPENSSL_wipe_cpu:
.L_OPENSSL_wipe_cpu_begin:
xorl %eax,%eax
xorl %edx,%edx
call .L015PIC_me_up
.L015PIC_me_up:
popl %ecx
leal OPENSSL_ia32cap_P-.L015PIC_me_up(%ecx),%ecx
movl (%ecx),%ecx
btl $1,(%ecx)
jnc .L016no_x87
andl $83886080,%ecx
cmpl $83886080,%ecx
jne .L017no_sse2
pxor %xmm0,%xmm0
pxor %xmm1,%xmm1
pxor %xmm2,%xmm2
pxor %xmm3,%xmm3
pxor %xmm4,%xmm4
pxor %xmm5,%xmm5
pxor %xmm6,%xmm6
pxor %xmm7,%xmm7
.L017no_sse2:
.long 4007259865,4007259865,4007259865,4007259865,2430851995
.L016no_x87:
leal 4(%esp),%eax
ret
.size OPENSSL_wipe_cpu,.-.L_OPENSSL_wipe_cpu_begin
.globl OPENSSL_atomic_add
.hidden OPENSSL_atomic_add
.type OPENSSL_atomic_add,@function
.align 16
OPENSSL_atomic_add:
.L_OPENSSL_atomic_add_begin:
movl 4(%esp),%edx
movl 8(%esp),%ecx
pushl %ebx
nop
movl (%edx),%eax
.L018spin:
leal (%eax,%ecx,1),%ebx
nop
.long 447811568
jne .L018spin
movl %ebx,%eax
popl %ebx
ret
.size OPENSSL_atomic_add,.-.L_OPENSSL_atomic_add_begin
.globl OPENSSL_indirect_call
.hidden OPENSSL_indirect_call
.type OPENSSL_indirect_call,@function
.align 16
OPENSSL_indirect_call:
.L_OPENSSL_indirect_call_begin:
pushl %ebp
movl %esp,%ebp
subl $28,%esp
movl 12(%ebp),%ecx
movl %ecx,(%esp)
movl 16(%ebp),%edx
movl %edx,4(%esp)
movl 20(%ebp),%eax
movl %eax,8(%esp)
movl 24(%ebp),%eax
movl %eax,12(%esp)
movl 28(%ebp),%eax
movl %eax,16(%esp)
movl 32(%ebp),%eax
movl %eax,20(%esp)
movl 36(%ebp),%eax
movl %eax,24(%esp)
call *8(%ebp)
movl %ebp,%esp
popl %ebp
ret
.size OPENSSL_indirect_call,.-.L_OPENSSL_indirect_call_begin
.globl OPENSSL_ia32_rdrand
.hidden OPENSSL_ia32_rdrand
.type OPENSSL_ia32_rdrand,@function
.align 16
OPENSSL_ia32_rdrand:
.L_OPENSSL_ia32_rdrand_begin:
movl $8,%ecx
.L019loop:
.byte 15,199,240
jc .L020break
loop .L019loop
.L020break:
cmpl $0,%eax
cmovel %ecx,%eax
ret
.size OPENSSL_ia32_rdrand,.-.L_OPENSSL_ia32_rdrand_begin
.hidden OPENSSL_ia32cap_P
#endif
linux-x86_64/crypto/bn/modexp512-x86_64.S deleted 100644 → 0
View file @ 0267d647
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